From b87327d1b9a0ec0c8b62694cb3697dcda1665ee2 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 12 Apr 2024 13:38:33 +0200 Subject: [PATCH] fix hierarchy -generate mode handling of cells --- passes/hierarchy/hierarchy.cc | 2 +- tests/various/hierarchy_generate.ys | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 tests/various/hierarchy_generate.ys diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 6fcda5d76..3ef04616f 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, { if (design->module(cell->type) != nullptr) continue; - if (cell->type.begins_with("$__")) + if (cell->type.begins_with("$") && !cell->type.begins_with("$__")) continue; for (auto &pattern : celltypes) if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) diff --git a/tests/various/hierarchy_generate.ys b/tests/various/hierarchy_generate.ys new file mode 100644 index 000000000..a4dc87a86 --- /dev/null +++ b/tests/various/hierarchy_generate.ys @@ -0,0 +1,19 @@ +read_verilog -icells <