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patch: unique heap

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This commit is contained in:
Emil J. Tywoniak 2026-05-14 17:43:46 +02:00
parent dbc7e33908
commit b7ea32dbee
3 changed files with 15 additions and 12 deletions
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16
kernel/unstable/patch.cc
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@ -17,10 +17,12 @@ using namespace RTLIL;
template class CellAdderMixin<Patch>; template class CellAdderMixin<Patch>;
Cell* Patch::addCell(IdString name, IdString type) { Cell* Patch::addCell(IdString name, IdString type) {
auto& cell = cells_.emplace_back(Cell::ConstructToken{}); cells_.emplace(cells_.end(), std::make_unique<Cell>(Cell::ConstructToken{}));
cell.name = std::move(name);
cell.type = type; Cell* cell = cells_.back().get();
return &cell; cell->name = std::move(name);
cell->type = type;
return cell;
} }
Wire* Patch::addWire(IdString name, int width) { Wire* Patch::addWire(IdString name, int width) {
@ -32,10 +34,10 @@ Wire* Patch::addWire(IdString name, int width) {
void Patch::patch() { void Patch::patch() {
for (auto& cell: cells_) { for (auto& cell: cells_) {
Cell* new_cell = mod->addCell(cell.name, &cell); Cell* new_cell = mod->addCell(cell->name, cell->type);
for (auto [port_name, sig] : new_cell->connections()) { for (auto [port_name, sig] : new_cell->connections()) {
log_assert(yosys_celltypes.cell_known(cell.type)); log_assert(yosys_celltypes.cell_known(cell->type));
auto dir = cell.port_dir(port_name); auto dir = cell->port_dir(port_name);
if (dir == PD_OUTPUT || dir == PD_INOUT) { if (dir == PD_OUTPUT || dir == PD_INOUT) {
for (auto chunk : sig.chunks()) { for (auto chunk : sig.chunks()) {
log_assert(chunk.is_wire()); log_assert(chunk.is_wire());

5
kernel/unstable/patch.h
View file

@ -19,8 +19,9 @@ protected:
public: public:
Module *mod; Module *mod;
SigMap map; SigMap map;
vector<Wire> wires_; vector<std::unique_ptr<Wire>> wires_;
vector<Cell> cells_; vector<std::unique_ptr<Cell>> cells_;
Cell* root;
vector<RTLIL::SigSig> connections_; vector<RTLIL::SigSig> connections_;

6
passes/cmds/test_patch.cc
View file

@ -13,13 +13,13 @@ struct TestPatchPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
(void) args; (void) args;
RTLIL::Patch patcher;
design->bufNormalize(); design->bufNormalize();
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
patcher.mod = module;
patcher.map = SigMap(module);
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) { if (cell->type == ID($add)) {
RTLIL::Patch patcher;
patcher.mod = module;
patcher.map = SigMap(module);
RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub)); RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
sub->connections_ = cell->connections(); sub->connections_ = cell->connections();
sub->parameters = cell->parameters; sub->parameters = cell->parameters;