From b7ea32dbee41ae59dcea74dd2a06175450f11e6f Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 14 May 2026 17:43:46 +0200
Subject: [PATCH] patch: unique heap

---
 kernel/unstable/patch.cc  | 16 +++++++++-------
 kernel/unstable/patch.h   |  5 +++--
 passes/cmds/test_patch.cc |  6 +++---
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc
index e1ca2aa96..8ef567db7 100644
--- a/kernel/unstable/patch.cc
+++ b/kernel/unstable/patch.cc
@@ -17,10 +17,12 @@ using namespace RTLIL;
 template class CellAdderMixin<Patch>;
 
 Cell* Patch::addCell(IdString name, IdString type) {
-	auto& cell = cells_.emplace_back(Cell::ConstructToken{});
-	cell.name = std::move(name);
-	cell.type = type;
-	return &cell;
+	cells_.emplace(cells_.end(), std::make_unique<Cell>(Cell::ConstructToken{}));
+
+	Cell* cell = cells_.back().get();
+	cell->name = std::move(name);
+	cell->type = type;
+	return cell;
 }
 
 Wire* Patch::addWire(IdString name, int width) {
@@ -32,10 +34,10 @@ Wire* Patch::addWire(IdString name, int width) {
 
 void Patch::patch() {
 	for (auto& cell: cells_) {
-		Cell* new_cell = mod->addCell(cell.name, &cell);
+		Cell* new_cell = mod->addCell(cell->name, cell->type);
 		for (auto [port_name, sig] : new_cell->connections()) {
-			log_assert(yosys_celltypes.cell_known(cell.type));
-			auto dir = cell.port_dir(port_name);
+			log_assert(yosys_celltypes.cell_known(cell->type));
+			auto dir = cell->port_dir(port_name);
 			if (dir == PD_OUTPUT || dir == PD_INOUT) {
 				for (auto chunk : sig.chunks()) {
 					log_assert(chunk.is_wire());
diff --git a/kernel/unstable/patch.h b/kernel/unstable/patch.h
index 287a739d6..bc902c2ee 100644
--- a/kernel/unstable/patch.h
+++ b/kernel/unstable/patch.h
@@ -19,8 +19,9 @@ protected:
 public:
 	Module *mod;
 	SigMap map;
-	vector<Wire> wires_;
-	vector<Cell> cells_;
+	vector<std::unique_ptr<Wire>> wires_;
+	vector<std::unique_ptr<Cell>> cells_;
+	Cell* root;
 
 	vector<RTLIL::SigSig> connections_;
 
diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc
index ba7ad851f..dc5270b3e 100644
--- a/passes/cmds/test_patch.cc
+++ b/passes/cmds/test_patch.cc
@@ -13,13 +13,13 @@ struct TestPatchPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		(void) args;
-		RTLIL::Patch patcher;
 		design->bufNormalize();
 		for (auto module : design->selected_modules()) {
-			patcher.mod = module;
-			patcher.map = SigMap(module);
 			for (auto cell : module->selected_cells()) {
 				if (cell->type == ID($add)) {
+					RTLIL::Patch patcher;
+					patcher.mod = module;
+					patcher.map = SigMap(module);
 					RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
 					sub->connections_ = cell->connections();
 					sub->parameters = cell->parameters;