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patch: unique heap
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parent
dbc7e33908
commit
b7ea32dbee
3 changed files with 15 additions and 12 deletions
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@ -17,10 +17,12 @@ using namespace RTLIL;
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template class CellAdderMixin<Patch>;
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Cell* Patch::addCell(IdString name, IdString type) {
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auto& cell = cells_.emplace_back(Cell::ConstructToken{});
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cell.name = std::move(name);
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cell.type = type;
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return &cell;
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cells_.emplace(cells_.end(), std::make_unique<Cell>(Cell::ConstructToken{}));
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Cell* cell = cells_.back().get();
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cell->name = std::move(name);
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cell->type = type;
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return cell;
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}
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Wire* Patch::addWire(IdString name, int width) {
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@ -32,10 +34,10 @@ Wire* Patch::addWire(IdString name, int width) {
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void Patch::patch() {
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for (auto& cell: cells_) {
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Cell* new_cell = mod->addCell(cell.name, &cell);
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Cell* new_cell = mod->addCell(cell->name, cell->type);
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for (auto [port_name, sig] : new_cell->connections()) {
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log_assert(yosys_celltypes.cell_known(cell.type));
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auto dir = cell.port_dir(port_name);
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log_assert(yosys_celltypes.cell_known(cell->type));
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auto dir = cell->port_dir(port_name);
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if (dir == PD_OUTPUT || dir == PD_INOUT) {
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for (auto chunk : sig.chunks()) {
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log_assert(chunk.is_wire());
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@ -19,8 +19,9 @@ protected:
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public:
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Module *mod;
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SigMap map;
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vector<Wire> wires_;
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vector<Cell> cells_;
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vector<std::unique_ptr<Wire>> wires_;
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vector<std::unique_ptr<Cell>> cells_;
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Cell* root;
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vector<RTLIL::SigSig> connections_;
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