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16 lines
265 B
Plaintext
16 lines
265 B
Plaintext
read_verilog -sv initval.v
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proc;;
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sat -seq 10 -prove-asserts
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output [1:0] o);
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(* init = 2'bx0 *)
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wire [1:0] o;
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assign o[1] = o[0];
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$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
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endmodule
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EOT
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sat -seq 1
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