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kernel: Add RTLIL::PortDir for a combined input and output flag

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This commit is contained in:
Jannis Harder 2025-08-14 16:13:43 +02:00
parent 9f62dd6e0e
commit b394629e3f
3 changed files with 34 additions and 0 deletions
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16
kernel/rtlil.cc
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@ -4241,6 +4241,22 @@ bool RTLIL::Cell::output(const RTLIL::IdString& portname) const
return false;
}
RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const
{
if (yosys_celltypes.cell_known(type))
return yosys_celltypes.cell_port_dir(type, portname);
if (module && module->design) {
RTLIL::Module *m = module->design->module(type);
if (m == nullptr)
return PortDir::PD_UNKNOWN;
RTLIL::Wire *w = m->wire(portname);
if (w == nullptr)
return PortDir::PD_UNKNOWN;
return PortDir(w->port_input + w->port_output * 2);
}
return PortDir::PD_UNKNOWN;
}
bool RTLIL::Cell::hasParam(const RTLIL::IdString& paramname) const
{
return parameters.count(paramname) != 0;