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WIP add placeholder $connect cell

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This commit is contained in:
Jannis Harder 2025-08-14 16:12:53 +02:00
parent 1dbf2df983
commit 9f62dd6e0e
3 changed files with 21 additions and 1 deletions
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1
kernel/celltypes.h
View file

@ -103,6 +103,7 @@ struct CellTypes
setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
setup_type(ID($connect), {ID::A, ID::Y}, {ID::A, ID::Y});
setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});

7
kernel/rtlil.cc
View file

@ -1475,6 +1475,13 @@ namespace {
return;
}
if (cell->type == ID($connect)) {
port(ID::A, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($not), ID($pos), ID($neg))) {
param_bool(ID::A_SIGNED);
port(ID::A, param(ID::A_WIDTH));

14
passes/opt/opt_clean.cc
View file

@ -601,11 +601,23 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf), ID($connect)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed);
if (a.has_const(State::Sz)) {
RTLIL::SigSpec new_a;
RTLIL::SigSpec new_y;
for (int i = 0; i < GetSize(a); i++) {
if (a[i] == State::Sz)
continue;
new_a.append(a[i]);
new_y.append(y[i]);
}
a = std::move(new_a);
y = std::move(new_y);
}
module->connect(y, a);
delcells.push_back(cell);
}