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WIP add placeholder $connect cell
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parent
1dbf2df983
commit
9f62dd6e0e
3 changed files with 21 additions and 1 deletions
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@ -103,6 +103,7 @@ struct CellTypes
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setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
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setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
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setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
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setup_type(ID($connect), {ID::A, ID::Y}, {ID::A, ID::Y});
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setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
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setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
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setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
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@ -1475,6 +1475,13 @@ namespace {
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return;
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}
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if (cell->type == ID($connect)) {
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port(ID::A, param(ID::WIDTH));
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port(ID::Y, param(ID::WIDTH));
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check_expected();
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return;
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}
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if (cell->type.in(ID($not), ID($pos), ID($neg))) {
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param_bool(ID::A_SIGNED);
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port(ID::A, param(ID::A_WIDTH));
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@ -601,11 +601,23 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
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std::vector<RTLIL::Cell*> delcells;
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for (auto cell : module->cells())
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if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
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if (cell->type.in(ID($pos), ID($_BUF_), ID($buf), ID($connect)) && !cell->has_keep_attr()) {
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bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
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RTLIL::SigSpec a = cell->getPort(ID::A);
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RTLIL::SigSpec y = cell->getPort(ID::Y);
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a.extend_u0(GetSize(y), is_signed);
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if (a.has_const(State::Sz)) {
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RTLIL::SigSpec new_a;
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RTLIL::SigSpec new_y;
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for (int i = 0; i < GetSize(a); i++) {
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if (a[i] == State::Sz)
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continue;
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new_a.append(a[i]);
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new_y.append(y[i]);
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}
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a = std::move(new_a);
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y = std::move(new_y);
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}
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module->connect(y, a);
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delcells.push_back(cell);
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}
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