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Completed ngspice digital example with verilog tb

This commit is contained in:
Uros Platise 2016-03-05 08:34:05 +01:00
parent b0ac32bc03
commit b34385ec92
5 changed files with 76 additions and 9 deletions

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#!/bin/bash
# iverlog simulation
echo "Doing Verilog simulation with iverilog"
iverilog -o dsn counter.v counter_tb.v
./dsn -lxt2
gtkwave counter_tb.vcd &
# yosys synthesis
set -ex
../../yosys counter_digital.ys
# requires ngspice with xspice support enabled:
ngspice testbench_digital.sp