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Improve SVA tests, add Makefile and scripts
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11 changed files with 110 additions and 9 deletions
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@ -8,5 +8,9 @@ module top (input logic clock, ctrl);
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end
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a_rw: assert property ( @(posedge clock) !(read && write) );
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`ifdef FAIL
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a_wr: assert property ( @(posedge clock) write |-> ready );
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`else
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a_wr: assert property ( @(posedge clock) write |=> ready );
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`endif
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endmodule
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