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17 lines
387 B
Systemverilog
17 lines
387 B
Systemverilog
module top (input logic clock, ctrl);
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logic read = 0, write = 0, ready = 0;
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always @(posedge clock) begin
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read <= !ctrl;
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write <= ctrl;
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ready <= write;
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end
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a_rw: assert property ( @(posedge clock) !(read && write) );
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`ifdef FAIL
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a_wr: assert property ( @(posedge clock) write |-> ready );
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`else
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a_wr: assert property ( @(posedge clock) write |=> ready );
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`endif
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endmodule
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