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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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271
techlibs/analogdevices/cells_sim.v
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@ -471,15 +471,15 @@ module FFRE (
input R input R
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q = INIT;
always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , posedge C, 31); $setup(D , posedge C, 31);
$setup(CE, posedge C, 122); $setup(CE, posedge C, 122);
$setup(R , posedge C, 128); $setup(R , posedge C, 128);
if (R) (posedge C => (Q : 1'b0)) = 280; if (R) (posedge C => (Q : 1'b0)) = 224;
if (!R && CE) (posedge C => (Q : D)) = 280; if (!R && CE) (posedge C => (Q : D)) = 224;
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
@ -487,10 +487,8 @@ module FFRE (
$setup(D , posedge C, 119); $setup(D , posedge C, 119);
$setup(CE, posedge C, 385); $setup(CE, posedge C, 385);
$setup(R , posedge C, 565); $setup(R , posedge C, 565);
// HACK: no clock-to-Q timings; using FFCE timing if (R) (posedge C => (Q : 1'b0)) = 672;
if (R) (posedge C => (Q : 1'b0)) = 689; if (!R && CE) (posedge C => (Q : D)) = 672;
// HACK: no clock-to-Q timings; using FFCE timing
if (!R && CE) (posedge C => (Q : D)) = 689;
endspecify endspecify
`endif `endif
endmodule endmodule
@ -505,15 +503,15 @@ module FFRE_N (
input R input R
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q = INIT;
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , negedge C, 31); $setup(D , negedge C, 31);
$setup(CE, negedge C, 122); $setup(CE, negedge C, 122);
$setup(R , negedge C, 128); $setup(R , negedge C, 128);
if (R) (negedge C => (Q : 1'b0)) = 280; if (R) (negedge C => (Q : 1'b0)) = 224;
if (!R && CE) (negedge C => (Q : D)) = 280; if (!R && CE) (negedge C => (Q : D)) = 224;
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
@ -521,14 +519,13 @@ module FFRE_N (
$setup(D , negedge C, 119); $setup(D , negedge C, 119);
$setup(CE, negedge C, 385); $setup(CE, negedge C, 385);
$setup(R , negedge C, 565); $setup(R , negedge C, 565);
// HACK: no clock-to-Q timings; using FFCE timing if (R) (negedge C => (Q : 1'b0)) = 672;
if (R) (negedge C => (Q : 1'b0)) = 689; if (!R && CE) (negedge C => (Q : D)) = 672;
// HACK: no clock-to-Q timings; using FFCE timing
if (!R && CE) (negedge C => (Q : D)) = 689;
endspecify endspecify
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module FFSE ( module FFSE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -538,30 +535,29 @@ module FFSE (
input S input S
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q = INIT;
always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , posedge C, 31); $setup(D , posedge C, 31);
$setup(CE, posedge C, 122); $setup(CE, posedge C, 122);
$setup(S , posedge C, 128); $setup(S , posedge C, 128);
if (S) (negedge C => (Q : 1'b1)) = 280; if (S) (posedge C => (Q : 1'b1)) = 224;
if (!S && CE) (posedge C => (Q : D)) = 280; if (!S && CE) (posedge C => (Q : D)) = 224;
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
$setup(D , posedge C, 119); $setup(D , posedge C, 119);
$setup(CE, posedge C, 385); $setup(CE, posedge C, 385);
$setup(S , posedge C, 584); $setup(S , posedge C, 565);
// HACK: no clock-to-Q timings; using FFCE timing if (S) (posedge C => (Q : 1'b1)) = 672;
if (S) (negedge C => (Q : 1'b1)) = 689; if (!S && CE) (posedge C => (Q : D)) = 672;
// HACK: no clock-to-Q timings; using FFCE timing
if (!S && CE) (posedge C => (Q : D)) = 689;
endspecify endspecify
`endif `endif
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module FFSE_N ( module FFSE_N (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -571,30 +567,29 @@ module FFSE_N (
input S input S
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q = INIT;
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , negedge C, 31); $setup(D , negedge C, 31);
$setup(CE, negedge C, 122); $setup(CE, negedge C, 122);
$setup(S , negedge C, 128); $setup(S , negedge C, 128);
if (S) (negedge C => (Q : 1'b1)) = 280; if (S) (negedge C => (Q : 1'b1)) = 224;
if (!S && CE) (negedge C => (Q : D)) = 280; if (!S && CE) (negedge C => (Q : D)) = 224;
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
$setup(D , negedge C, 119); $setup(D , negedge C, 119);
$setup(CE, negedge C, 385); $setup(CE, negedge C, 385);
$setup(S , negedge C, 584); $setup(S , negedge C, 565);
// HACK: no clock-to-Q timings; using FFCE timing if (S) (negedge C => (Q : 1'b1)) = 672;
if (S) (negedge C => (Q : 1'b1)) = 689; if (!S && CE) (negedge C => (Q : D)) = 672;
// HACK: no clock-to-Q timings; using FFCE timing
if (!S && CE) (negedge C => (Q : D)) = 689;
endspecify endspecify
`endif `endif
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFCE ( module FFCE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -604,24 +599,33 @@ module FFCE (
input D input D
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q = INIT;
always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , posedge C, 31); $setup(D , posedge C, 31);
$setup(CE, posedge C, 122); $setup(CE, posedge C, 122);
$setup(CLR, posedge C, 0 /* missing? */);
if (!CLR && CE) (posedge C => (Q : D)) = 280; if (!CLR && CE) (posedge C => (Q : D)) = 280;
`ifdef YOSYS
if (CLR) (CLR => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
$setup(D , posedge C, 119); $setup(D , posedge C, 119);
$setup(CE, posedge C, 385); $setup(CE, posedge C, 385);
$setup(CLR, posedge C, 0 /* missing? */);
if (!CLR && CE) (posedge C => (Q : D)) = 689; if (!CLR && CE) (posedge C => (Q : D)) = 689;
`ifdef YOSYS
if (CLR) (CLR => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFCE_N ( module FFCE_N (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -631,20 +635,28 @@ module FFCE_N (
input D input D
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q = INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , negedge C, 31); $setup(D, negedge C, 31);
$setup(CE, negedge C, 122); $setup(CE, negedge C, 122);
$setup(CLR, negedge C, 0 /* missing? */);
if (!CLR && CE) (negedge C => (Q : D)) = 280; if (!CLR && CE) (negedge C => (Q : D)) = 280;
`ifdef YOSYS
if (CLR) (CLR => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
$setup(D , negedge C, 119); $setup(D, negedge C, 119);
$setup(CE, negedge C, 385); $setup(CE, negedge C, 385);
$setup(CLR, negedge C, 0 /* missing? */);
if (!CLR && CE) (negedge C => (Q : D)) = 689; if (!CLR && CE) (negedge C => (Q : D)) = 689;
`ifdef YOSYS
if (CLR) (CLR => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
endmodule endmodule
@ -658,21 +670,28 @@ module FFPE (
input D input D
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q = INIT;
always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , posedge C, 31); $setup(D, posedge C, 31);
$setup(CE, posedge C, 122); $setup(CE, posedge C, 122);
if (!PRE && CE) (posedge C => (Q : D)) = 291; $setup(PRE, posedge C, 0 /* missing? */);
if (!PRE && CE) (posedge C => (Q : D)) = 224;
`ifdef YOSYS
if (PRE) (PRE => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
$setup(D , posedge C, 119); $setup(D, posedge C, 119);
$setup(CE, posedge C, 385); $setup(CE, posedge C, 385);
// HACK: no clock-to-Q timings; using FFPE_N timing $setup(PRE, posedge C, 0 /* missing? */);
if (!PRE && CE) (posedge C => (Q : D)) = 712; if (!PRE && CE) (posedge C => (Q : D)) = 672;
`ifdef YOSYS
if (PRE) (PRE => Q) = 0 /* missing? */;
`endif
endspecify endspecify
`endif `endif
endmodule endmodule
@ -686,22 +705,28 @@ module FFPE_N (
input D input D
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q = INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
$setup(D , negedge C, 31); $setup(D, negedge C, 28);
$setup(CE , negedge C, 122); $setup(CE, negedge C, 28);
$setup(PRE, negedge C, 28);
if (!PRE && CE) (negedge C => (Q : D)) = 291; if (!PRE && CE) (negedge C => (Q : D)) = 291;
`ifdef YOSYS
if (PRE) (PRE => Q) = 57;
`endif
endspecify endspecify
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
// HACK: no D setup time; using FFPE timing $setup(D, negedge C, 84);
$setup(D , negedge C, 119); $setup(CE, negedge C, 84);
// HACK: no CE setup time; using FFPE timing $setup(PRE, negedge C, 84);
$setup(CE, negedge C, 385);
if (!PRE && CE) (negedge C => (Q : D)) = 712; if (!PRE && CE) (negedge C => (Q : D)) = 712;
`ifdef YOSYS
if (PRE) (PRE => Q) = 57;
`endif
endspecify endspecify
`endif `endif
endmodule endmodule
@ -726,14 +751,13 @@ module RAMS32X1 (
always @(posedge WCLK) if (WE) mem[a] <= D; always @(posedge WCLK) if (WE) mem[a] <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
// HACK: no setup timing $setup(A0, posedge WCLK, 28);
$setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 28);
$setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 28);
$setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 28);
$setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 28);
$setup(A4, posedge WCLK, 0); $setup(D, posedge WCLK, 28);
$setup(D, posedge WCLK, 0); $setup(WE, posedge WCLK, 28);
$setup(WE, posedge WCLK, 0);
(A0 => O) = 63; (A0 => O) = 63;
(A1 => O) = 63; (A1 => O) = 63;
(A2 => O) = 63; (A2 => O) = 63;
@ -744,14 +768,13 @@ module RAMS32X1 (
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
// HACK: no setup timing $setup(A0, posedge WCLK, 84);
$setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 84);
$setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 84);
$setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 84);
$setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 84);
$setup(A4, posedge WCLK, 0); $setup(D, posedge WCLK, 84);
$setup(D, posedge WCLK, 0); $setup(WE, posedge WCLK, 84);
$setup(WE, posedge WCLK, 0);
(A0 => O) = 168; (A0 => O) = 168;
(A1 => O) = 168; (A1 => O) = 168;
(A2 => O) = 168; (A2 => O) = 168;
@ -778,15 +801,14 @@ module RAMS64X1 (
always @(posedge WCLK) if (WE) mem[a] <= D; always @(posedge WCLK) if (WE) mem[a] <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
// HACK: no setup timing $setup(A0, posedge WCLK, 28);
$setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 28);
$setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 28);
$setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 28);
$setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 28);
$setup(A4, posedge WCLK, 0); $setup(A5, posedge WCLK, 28);
$setup(A5, posedge WCLK, 0); $setup(D, posedge WCLK, 28);
$setup(D, posedge WCLK, 0); $setup(WE, posedge WCLK, 28);
$setup(WE, posedge WCLK, 0);
(A0 => O) = 161; (A0 => O) = 161;
(A1 => O) = 161; (A1 => O) = 161;
(A2 => O) = 161; (A2 => O) = 161;
@ -798,15 +820,14 @@ module RAMS64X1 (
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
// HACK: no setup timing $setup(A0, posedge WCLK, 84);
$setup(A0, posedge WCLK, 0); $setup(A1, posedge WCLK, 84);
$setup(A1, posedge WCLK, 0); $setup(A2, posedge WCLK, 84);
$setup(A2, posedge WCLK, 0); $setup(A3, posedge WCLK, 84);
$setup(A3, posedge WCLK, 0); $setup(A4, posedge WCLK, 84);
$setup(A4, posedge WCLK, 0); $setup(A5, posedge WCLK, 84);
$setup(A5, posedge WCLK, 0); $setup(D, posedge WCLK, 84);
$setup(D, posedge WCLK, 0); $setup(WE, posedge WCLK, 84);
$setup(WE, posedge WCLK, 0);
(A0 => O) = 466; (A0 => O) = 466;
(A1 => O) = 466; (A1 => O) = 466;
(A2 => O) = 466; (A2 => O) = 466;
@ -832,26 +853,26 @@ module RAMD32X1 (
); );
parameter INIT = 32'h0; parameter INIT = 32'h0;
wire [4:0] a = {A4, A3, A2, A1, A0}; wire [4:0] a = {A4, A3, A2, A1, A0};
wire [4:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [31:0] mem = INIT; reg [31:0] mem = INIT;
assign SPO = mem[a]; assign SPO = mem[a];
assign DPO = mem[dpra]; assign DPO = mem[dpra];
always @(posedge WCLK) if (WE) mem[a] <= D; always @(posedge WCLK) if (WE) mem[a] <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
// HACK: no setup timing // HACK: partial setup timing
$setup(A0, posedge WCLK, 0); $setup(A0, posedge WCLK, 28);
$setup(A1, posedge WCLK, 0); $setup(A1, posedge WCLK, 28);
$setup(A2, posedge WCLK, 0); $setup(A2, posedge WCLK, 28);
$setup(A3, posedge WCLK, 0); $setup(A3, posedge WCLK, 28);
$setup(A4, posedge WCLK, 0); $setup(A4, posedge WCLK, 28);
$setup(DPRA0, posedge WCLK, 0); $setup(DPRA0, posedge WCLK, 0);
$setup(DPRA1, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0);
$setup(DPRA2, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0);
$setup(DPRA3, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0);
$setup(DPRA4, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0);
$setup(D, posedge WCLK, 0); $setup(D, posedge WCLK, 28);
$setup(WE, posedge WCLK, 0); $setup(WE, posedge WCLK, 28);
// HACK: No timing arcs for SPO; using ones for DPO // HACK: No timing arcs for SPO; using ones for DPO
// (are we meant to use the single-port timings here?) // (are we meant to use the single-port timings here?)
(A0 => SPO) = 66; (A0 => SPO) = 66;
@ -870,19 +891,19 @@ module RAMD32X1 (
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
// HACK: no setup timing // HACK: partial setup timing
$setup(A0, posedge WCLK, 0); $setup(A0, posedge WCLK, 84);
$setup(A1, posedge WCLK, 0); $setup(A1, posedge WCLK, 84);
$setup(A2, posedge WCLK, 0); $setup(A2, posedge WCLK, 84);
$setup(A3, posedge WCLK, 0); $setup(A3, posedge WCLK, 84);
$setup(A4, posedge WCLK, 0); $setup(A4, posedge WCLK, 84);
$setup(DPRA0, posedge WCLK, 0); $setup(DPRA0, posedge WCLK, 0);
$setup(DPRA1, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0);
$setup(DPRA2, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0);
$setup(DPRA3, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0);
$setup(DPRA4, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0);
$setup(D, posedge WCLK, 0); $setup(D, posedge WCLK, 84);
$setup(WE, posedge WCLK, 0); $setup(WE, posedge WCLK, 84);
// HACK: No timing arcs for SPO; using ones for DPO // HACK: No timing arcs for SPO; using ones for DPO
// (are we meant to use the single-port timings here?) // (are we meant to use the single-port timings here?)
(A0 => SPO) = 142; (A0 => SPO) = 142;
@ -920,21 +941,21 @@ module RAMD64X1 (
always @(posedge WCLK) if (WE) mem[a] <= D; always @(posedge WCLK) if (WE) mem[a] <= D;
`ifdef IS_T16FFC `ifdef IS_T16FFC
specify specify
// HACK: no setup timing // HACK: partial setup timing
$setup(A0, posedge WCLK, 0); $setup(A0, posedge WCLK, 28);
$setup(A1, posedge WCLK, 0); $setup(A1, posedge WCLK, 28);
$setup(A2, posedge WCLK, 0); $setup(A2, posedge WCLK, 28);
$setup(A3, posedge WCLK, 0); $setup(A3, posedge WCLK, 28);
$setup(A4, posedge WCLK, 0); $setup(A4, posedge WCLK, 28);
$setup(A5, posedge WCLK, 0); $setup(A5, posedge WCLK, 28);
$setup(DPRA0, posedge WCLK, 0); $setup(DPRA0, posedge WCLK, 0);
$setup(DPRA1, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0);
$setup(DPRA2, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0);
$setup(DPRA3, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0);
$setup(DPRA4, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0);
$setup(DPRA5, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0);
$setup(D, posedge WCLK, 0); $setup(D, posedge WCLK, 28);
$setup(WE, posedge WCLK, 0); $setup(WE, posedge WCLK, 28);
(A0 => SPO) = 161; (A0 => SPO) = 161;
(A1 => SPO) = 161; (A1 => SPO) = 161;
(A2 => SPO) = 161; (A2 => SPO) = 161;
@ -953,21 +974,21 @@ module RAMD64X1 (
`endif `endif
`ifdef IS_T40LP `ifdef IS_T40LP
specify specify
// HACK: no setup timing // HACK: partial setup timing
$setup(A0, posedge WCLK, 0); $setup(A0, posedge WCLK, 84);
$setup(A1, posedge WCLK, 0); $setup(A1, posedge WCLK, 84);
$setup(A2, posedge WCLK, 0); $setup(A2, posedge WCLK, 84);
$setup(A3, posedge WCLK, 0); $setup(A3, posedge WCLK, 84);
$setup(A4, posedge WCLK, 0); $setup(A4, posedge WCLK, 84);
$setup(A5, posedge WCLK, 0); $setup(A5, posedge WCLK, 84);
$setup(DPRA0, posedge WCLK, 0); $setup(DPRA0, posedge WCLK, 0);
$setup(DPRA1, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0);
$setup(DPRA2, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0);
$setup(DPRA3, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0);
$setup(DPRA4, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0);
$setup(DPRA5, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0);
$setup(D, posedge WCLK, 0); $setup(D, posedge WCLK, 84);
$setup(WE, posedge WCLK, 0); $setup(WE, posedge WCLK, 84);
(A0 => SPO) = 466; (A0 => SPO) = 466;
(A1 => SPO) = 466; (A1 => SPO) = 466;
(A2 => SPO) = 466; (A2 => SPO) = 466;
@ -1091,7 +1112,7 @@ parameter FF_SYNC_RST = 1'b0;
specify specify
if (!REG_A) (A *> P) = 1000; if (!REG_A) (A *> P) = 1000;
if (!REG_B) (B *> P) = 1000; if (!REG_B) (B *> P) = 1000;
if (!REG_D[0]) (D *> P) = 1000; if (!REG_D) (D *> P) = 1000;
endspecify endspecify
// Much of this functionality is TODO. // Much of this functionality is TODO.
@ -1112,7 +1133,7 @@ module RBRAM #(
parameter DATA_WIDTH = 40, parameter DATA_WIDTH = 40,
parameter ADDR_WIDTH = 12, parameter ADDR_WIDTH = 12,
parameter WE_WIDTH = 20, parameter WE_WIDTH = 20,
parameter PERR_WIDTH = 4, parameter PERR_WIDTH = 4
) ( ) (
output [DATA_WIDTH-1:0] QA, output [DATA_WIDTH-1:0] QA,
input [DATA_WIDTH-1:0] DA, input [DATA_WIDTH-1:0] DA,
@ -1137,7 +1158,7 @@ module RBRAM #(
output MBEA, output MBEA,
output MBEB, output MBEB,
input SLP, input SLP,
input PD, input PD
); );
endmodule endmodule
@ -1152,7 +1173,7 @@ module RBRAM2 #(
parameter DATA_WIDTH = 40, parameter DATA_WIDTH = 40,
parameter ADDR_WIDTH = 13, parameter ADDR_WIDTH = 13,
parameter WE_WIDTH = 20, parameter WE_WIDTH = 20,
parameter PERR_WIDTH = 4, parameter PERR_WIDTH = 4
) ( ) (
output [DATA_WIDTH-1:0] QA, output [DATA_WIDTH-1:0] QA,
input [DATA_WIDTH-1:0] DA, input [DATA_WIDTH-1:0] DA,
@ -1177,7 +1198,7 @@ module RBRAM2 #(
output MBEA, output MBEA,
output MBEB, output MBEB,
input SLP, input SLP,
input PD, input PD
); );
endmodule endmodule

142
tests/arch/analogdevices/abc9_dff.ys
View file

@ -1,142 +0,0 @@
logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
logger -nowarn "Ignoring boxed module .*\."
read_verilog <<EOT
module top(input C, D, output [7:0] Q);
FFRE /*#(.INIT(0))*/ fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
FFSE #(.INIT(0)) fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
FFCE #(.INIT(0)) fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
FFPE #(.INIT(0)) fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
FFRE_N #(.INIT(0)) fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
FFSE_N #(.INIT(0)) fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
FFCE_N #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
FFPE_N #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
endmodule
EOT
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 6 t:FF*
select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
design -reset
read_verilog <<EOT
module top(input C, D, output [7:0] Q);
FFRE #(.INIT(0)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
FFSE #(.INIT(0)) fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
FFCE #(.INIT(0)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
FFPE #(.INIT(0)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
FFRE_N /*#(.INIT(0))*/ fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
FFSE_N #(.INIT(0)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
FFCE_N #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FFPE_N #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 4 t:FF*
select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
design -reset
read_verilog <<EOT
module top(input C, D, output [7:0] Q);
FFRE #(.INIT(1)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
FFSE /*#(.INIT(1))*/ fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
FFCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
FFPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
FFRE_N #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
FFSE_N #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
FFCE_N /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FFPE_N #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
logger -expect warning "Whitebox '\$paramod\\FFRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox '\$paramod\\FFRE_N\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox 'FFSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
logger -expect warning "Whitebox '\$paramod\\FFSE_N\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 8 t:FF*
design -reset
read_verilog <<EOT
module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1);
always @(posedge clk or posedge clr)
if (clr)
q0 <= 1'b0;
else
q0 <= ~q0;
always @(posedge clk or posedge pre)
if (pre)
q1 <= 1'b1;
else
q1 <= ~q1;
endmodule
EOT
proc
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FFCE
select -assert-count 1 t:FFPE
select -assert-count 2 t:INV
select -assert-count 0 t:FF* t:INV %% t:* %D
design -reset
read_verilog <<EOT
module top(input clk, input d, output q);
reg r;
always @(posedge clk) begin
r <= d;
end
assign q = ~r;
endmodule
EOT
proc
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FFRE %co w:r %i
design -reset
read_verilog <<EOT
module top(input clk, input a, b, output reg q1, output q2);
reg r;
always @(posedge clk) begin
q1 <= a | b;
r <= ~(~a & ~b);
end
assign q2 = r;
endmodule
EOT
proc
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 1 t:FFRE %co %a w:r %i
design -reset
read_verilog <<EOT
module top(input clk, input a, b, output o);
reg r1, r2;
always @(posedge clk) begin
r1 <= a | b;
r2 <= ~(~a & ~b);
end
assign o = r1 | r2;
endmodule
EOT
proc
read_verilog -lib +/analogdevices/cells_sim.v
equiv_opt -assert -multiclock -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad -noclkbuf
logger -expect-no-warnings

4
tests/arch/analogdevices/add_sub.ys
View file

@ -9,5 +9,5 @@ cd top # Constrain all select calls below inside the top module
stat stat
select -assert-count 8 t:LUT2 select -assert-count 8 t:LUT2
select -assert-count 2 t:CRY4 select -assert-count 2 t:CRY4
select -assert-none t:LUT2 t:CRY4 %% t:* %D select -assert-count 2 t:CRY4INIT
select -assert-none t:LUT2 t:CRY4 t:CRY4INIT %% t:* %D

16
tests/arch/analogdevices/adffs.ys
View file

@ -6,10 +6,9 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFCE select -assert-count 1 t:FFCE
select -assert-none t:BUFG t:FFCE %% t:* %D select -assert-none t:FFCE %% t:* %D
design -load read design -load read
@ -18,11 +17,10 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFCE select -assert-count 1 t:FFCE
select -assert-count 1 t:INV select -assert-count 1 t:LUT1
select -assert-none t:BUFG t:FFCE t:INV %% t:* %D select -assert-none t:FFCE t:LUT1 %% t:* %D
design -load read design -load read
@ -31,11 +29,10 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE select -assert-count 1 t:FFRE
select -assert-count 1 t:LUT2 select -assert-count 1 t:LUT2
stat stat
select -assert-none t:BUFG t:FFRE t:LUT2 %% t:* %D select -assert-none t:FFRE t:LUT2 %% t:* %D
design -load read design -load read
@ -44,8 +41,7 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE_N select -assert-count 1 t:FFRE_N
select -assert-count 1 t:INV select -assert-count 1 t:LUT1
select -assert-none t:BUFG t:FFRE_N t:INV %% t:* %D select -assert-none t:FFRE_N t:LUT1 %% t:* %D

16
tests/arch/analogdevices/asym_ram_sdp.ys
View file

@ -1,44 +1,44 @@
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2
# w4b | r16b # w4b | r16b
design -reset design -reset
read_verilog asym_ram_sdp_read_wider.v read_verilog asym_ram_sdp_read_wider.v
synth_analogdevices -top asym_ram_sdp_read_wider -noiopad synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# w8b | r16b # w8b | r16b
design -reset design -reset
read_verilog asym_ram_sdp_read_wider.v read_verilog asym_ram_sdp_read_wider.v
chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_read_wider -noiopad synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# w4b | r32b # w4b | r32b
design -reset design -reset
read_verilog asym_ram_sdp_read_wider.v read_verilog asym_ram_sdp_read_wider.v
chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_read_wider -noiopad synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 2 t:RBRAM2
# w16b | r4b # w16b | r4b
design -reset design -reset
read_verilog asym_ram_sdp_write_wider.v read_verilog asym_ram_sdp_write_wider.v
synth_analogdevices -top asym_ram_sdp_write_wider -noiopad synth_analogdevices -top asym_ram_sdp_write_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# w16b | r8b # w16b | r8b
design -reset design -reset
read_verilog asym_ram_sdp_write_wider.v read_verilog asym_ram_sdp_write_wider.v
chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_write_wider -noiopad synth_analogdevices -top asym_ram_sdp_write_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# w32b | r4b # w32b | r4b
design -reset design -reset
read_verilog asym_ram_sdp_write_wider.v read_verilog asym_ram_sdp_write_wider.v
chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_write_wider -noiopad synth_analogdevices -top asym_ram_sdp_write_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# w4b | r24b # w4b | r24b
design -reset design -reset
@ -46,5 +46,5 @@ read_verilog asym_ram_sdp_read_wider.v
chparam -set SIZEA 768 chparam -set SIZEA 768
chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_read_wider -noiopad synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
select -assert-count 1 t:RAMB18E1 select -assert-count 2 t:RBRAM2

1
tests/arch/analogdevices/asym_ram_sdp_read_wider.v
View file

@ -46,6 +46,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
localparam RATIO = maxWIDTH / minWIDTH; localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO); localparam log2RATIO = log2(RATIO);
(* ram_style="block" *)
reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB; reg [WIDTHB-1:0] readB;

1
tests/arch/analogdevices/asym_ram_sdp_write_wider.v
View file

@ -46,6 +46,7 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
localparam RATIO = maxWIDTH / minWIDTH; localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO); localparam log2RATIO = log2(RATIO);
(* ram_style="block" *)
reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB; reg [WIDTHB-1:0] readB;

12
tests/arch/analogdevices/attributes_test.ys
View file

@ -3,7 +3,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top block_ram hierarchy -top block_ram
synth_analogdevices -top block_ram -noiopad synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module cd block_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1 # select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
# Check that distributed memory without parameters is not modified # Check that distributed memory without parameters is not modified
design -reset design -reset
@ -11,7 +11,8 @@ read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top distributed_ram hierarchy -top distributed_ram
synth_analogdevices -top distributed_ram -noiopad synth_analogdevices -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAM32M select -assert-count 8 t:RAMS64X1
select -assert-count 8 t:FFRE
# Set ram_style distributed to blockram memory; will be implemented as distributed # Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset design -reset
@ -19,7 +20,8 @@ read_verilog ../common/memory_attributes/attributes_test.v
setattr -set ram_style "distributed" block_ram/m:* setattr -set ram_style "distributed" block_ram/m:*
synth_analogdevices -top block_ram -noiopad synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module cd block_ram # Constrain all select calls below inside the top module
select -assert-count 64 t:RAM64X1S select -assert-count 64 t:RAMS64X1
select -assert-count 4 t:FFRE
# Set synthesis, logic_block to blockram memory; will be implemented as distributed # Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset design -reset
@ -27,11 +29,11 @@ read_verilog ../common/memory_attributes/attributes_test.v
setattr -set logic_block 1 block_ram/m:* setattr -set logic_block 1 block_ram/m:*
synth_analogdevices -top block_ram -noiopad synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RAMB18E1 select -assert-count 0 t:RBRAM2
# Set ram_style block to a distributed memory; will be implemented as blockram # Set ram_style block to a distributed memory; will be implemented as blockram
design -reset design -reset
read_verilog ../common/memory_attributes/attributes_test.v read_verilog ../common/memory_attributes/attributes_test.v
synth_analogdevices -top distributed_ram_manual -noiopad synth_analogdevices -top distributed_ram_manual -noiopad
cd distributed_ram_manual # Constrain all select calls below inside the top module cd distributed_ram_manual # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1 # select -assert-count 1 t:RBRAM2 # This gets implemented in logic instead

26
tests/arch/analogdevices/blockram.ys
View file

@ -1,32 +1,35 @@
### TODO: Not running equivalence checking because BRAM models does not exists ### TODO: Not running equivalence checking because BRAM models does not exists
### currently. Checking instance counts instead. ### currently. Checking instance counts instead.
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp
setattr -set ram_style "block" sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
design -reset design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
setattr -set ram_style "block" sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
design -reset design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
setattr -set ram_style "block" sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
design -reset design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
# Anything memory bits < 1024 -> LUTRAM # Anything memory bits < 1024 -> LUTRAM
design -reset design -reset
@ -34,8 +37,9 @@ read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1 select -assert-count 0 t:RBRAM2
select -assert-count 4 t:RAM64M select -assert-count 8 t:RAMD64X1
select -assert-count 2 t:FFRE
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
design -reset design -reset
@ -43,7 +47,7 @@ read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB36E1 select -assert-count 1 t:RBRAM2
### With parameters ### With parameters
@ -54,7 +58,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory setattr -set ram_style "block" m:memory
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2
design -reset design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
@ -62,7 +66,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory setattr -set logic_block 1 m:memory
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1 select -assert-count 0 t:RBRAM2
design -reset design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
@ -70,4 +74,4 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory setattr -set ram_style "block" m:memory
synth_analogdevices -top sync_ram_sdp -noiopad synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RBRAM2

4
tests/arch/analogdevices/bug1460.ys
View file

@ -30,5 +30,5 @@ EOT
synth_analogdevices -noiopad synth_analogdevices -noiopad
cd register_file cd register_file
select -assert-count 33 t:RAM32M select -assert-count 192 t:RAMD32X1
select -assert-none t:* t:BUFG %d t:RAM32M %d select -assert-none t:RAMD32X1 %% t:* %D

19
tests/arch/analogdevices/bug1605.ys
View file

@ -1,19 +0,0 @@
read_verilog <<EOT
module top(inout io);
wire in;
wire t;
wire o;
IOBUF IOBUF(
.I(in),
.T(t),
.IO(io),
.O(o)
);
endmodule
EOT
synth_analogdevices
cd top
select -assert-count 1 t:IOBUF
select -assert-none t:* t:IOBUF %d

13
tests/arch/analogdevices/bug3670.v
View file

@ -1,13 +0,0 @@
module bug3670(input we, output [31:0] o1, o2, output o3);
// Completely missing port connections, where first affected port
// (ADDRARDADDR) has a $setup delay
RAMB36E1 ram1(.DOADO(o1));
// Under-specified input port connections (WEA is 4 bits) which
// has a $setup delay
RAMB36E1 ram2(.WEA(we), .DOADO(o2));
// Under-specified output port connections (DOADO is 32 bits)
// with clk-to-q delay
RAMB36E1 ram3(.DOADO(o3));
endmodule

3
tests/arch/analogdevices/bug3670.ys
View file

@ -1,3 +0,0 @@
read_verilog bug3670.v
read_verilog -lib -specify +/analogdevices/cells_sim.v
abc9

6
tests/arch/analogdevices/counter.ys
View file

@ -6,8 +6,8 @@ equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevic
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FFCE select -assert-count 8 t:FFCE
select -assert-count 1 t:INV select -assert-count 1 t:LUT1
select -assert-count 2 t:CRY4 select -assert-count 2 t:CRY4
select -assert-none t:BUFG t:FFCE t:INV t:CRY4 %% t:* %D select -assert-count 1 t:CRY4INIT
select -assert-none t:FFCE t:LUT1 t:CRY4 t:CRY4INIT %% t:* %D

12
tests/arch/analogdevices/dffs.ys
View file

@ -6,9 +6,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D select -assert-none t:FFRE %% t:* %D
design -load read design -load read
@ -17,9 +16,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D select -assert-none t:FFRE %% t:* %D
design -load read design -load read
@ -28,9 +26,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D select -assert-none t:FFRE %% t:* %D
design -load read design -load read
@ -39,7 +36,6 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D select -assert-none t:FFRE %% t:* %D

22
tests/arch/analogdevices/dsp_abc9.ys
View file

@ -20,19 +20,19 @@ EOT
synth_analogdevices synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine opt -full -fine
select -assert-count 1 t:$mul select -assert-count 2 t:$mul
select -assert-count 0 t:* t:$mul %D select -assert-count 0 t:* t:$mul %D
design -reset design -reset
read_verilog -icells -formal <<EOT read_verilog -icells -formal <<EOT
module top(output [42:0] P); module top(output [43:0] P);
\$__MUL25X18 mul (.A(42), .B(42), .Y(P)); \$__MUL22X22 mul (.A(42), .B(42), .Y(P));
assert property (P == 42*42); assert property (P == 42*42);
endmodule endmodule
EOT EOT
async2sync async2sync
techmap -map +/analogdevices/xc7_dsp_map.v techmap -map +/analogdevices/dsp_map.v
verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1 verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_analogdevices synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v techmap -autoproc -wb -map +/analogdevices/cells_sim.v
@ -40,17 +40,3 @@ opt -full -fine
select -assert-count 0 t:* t:$assert %d select -assert-count 0 t:* t:$assert %d
sat -verify -prove-asserts sat -verify -prove-asserts
design -reset
read_verilog <<EOT
module top(input signed [29:0] A, input signed [17:0] B, output signed [47:0] P);
wire [47:0] casc;
DSP48E1 #(.AREG(1)) u1(.A(A), .B(B), .PCOUT(casc));
DSP48E1 #(.AREG(1)) u2(.A(A), .B(B), .PCIN(casc), .P(P));
endmodule
EOT
synth_analogdevices -run :prepare
abc9
clean
check
logger -expect-no-warnings

5
tests/arch/analogdevices/fsm.ys
View file

@ -12,10 +12,9 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FFRE select -assert-count 6 t:FFRE
select -assert-count 1 t:INV select -assert-count 1 t:LUT1
select -assert-count 1 t:LUT3 select -assert-count 1 t:LUT3
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
select -assert-count 5 t:LUT5 select -assert-count 5 t:LUT5
select -assert-none t:BUFG t:FFRE t:INV t:LUT3 t:LUT4 t:LUT5 %% t:* %D select -assert-none t:FFRE t:LUT1 t:LUT3 t:LUT4 t:LUT5 %% t:* %D

4
tests/arch/analogdevices/logic.ys
View file

@ -5,7 +5,7 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:INV select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT2 select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D

8
tests/arch/analogdevices/lutram.ys
View file

@ -13,8 +13,8 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
design -load postopt design -load postopt
cd lutram_1w1r cd lutram_1w1r
select -assert-count 8 t:FFRE select -assert-count 8 t:FFRE
select -assert-count 8 t:RAMS32X1 select -assert-count 8 t:RAMS64X1
select -assert-none t:FFRE t:RAMS32X1 %% t:* %D select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
design -reset design -reset
@ -90,8 +90,8 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
design -load postopt design -load postopt
cd lutram_1w1r cd lutram_1w1r
select -assert-count 6 t:FFRE select -assert-count 6 t:FFRE
select -assert-count 6 t:RAMS32X1 select -assert-count 6 t:RAMS64X1
select -assert-none t:FFRE t:RAMS32X1 %% t:* %D select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
design -reset design -reset

6
tests/arch/analogdevices/macc.sh
View file

@ -1,6 +0,0 @@
../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc
../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc

84
tests/arch/analogdevices/macc.v
View file

@ -1,84 +0,0 @@
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: HDL_Coding_Techniques/multipliers/multipliers4.v
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
//
module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0;
reg sload_reg = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT-1:0] adder_out = 0, old_result;
always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule
// Adapted variant of above
module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk,
input ce,
input rst,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out,
output overflow
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT:0] adder_out = 0;
reg overflow_reg = 0;
always @(posedge clk) begin
//if (ce)
begin
a_reg <= a;
b_reg <= b;
a_reg2 <= a_reg;
b_reg2 <= b_reg;
mult_reg <= a_reg2 * b_reg2;
// Store accumulation result into a register
adder_out <= adder_out + mult_reg;
overflow_reg <= overflow;
end
if (rst) begin
a_reg <= 0;
a_reg2 <= 0;
b_reg <= 0;
b_reg2 <= 0;
mult_reg <= 0;
adder_out <= 0;
overflow_reg <= 1'b0;
end
end
assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
// Output accumulation result
assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
endmodule

32
tests/arch/analogdevices/macc.ys
View file

@ -1,32 +0,0 @@
read_verilog macc.v
design -save read
hierarchy -top macc
proc
#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FFRE t:DSP48E1 %% t:* %D
design -load read
hierarchy -top macc2
proc
#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc2 # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 1 t:FFRE
select -assert-count 1 t:LUT2
select -assert-count 40 t:LUT3
select -assert-none t:BUFG t:DSP48E1 t:FFRE t:LUT2 t:LUT3 %% t:* %D

96
tests/arch/analogdevices/macc_tb.v
View file

@ -1,96 +0,0 @@
`timescale 1ns / 1ps
module testbench;
parameter SIZEIN = 16, SIZEOUT = 40;
reg clk, ce, rst;
reg signed [SIZEIN-1:0] a, b;
output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
output REF_overflow, overflow;
integer errcount = 0;
reg ERROR_FLAG = 0;
task clkcycle;
begin
#5;
clk = ~clk;
#10;
clk = ~clk;
#2;
ERROR_FLAG = 0;
if (REF_accum_out !== accum_out) begin
$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
if (REF_overflow !== overflow) begin
$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
#3;
end
endtask
initial begin
//$dumpfile("test_macc.vcd");
//$dumpvars(0, testbench);
#2;
clk = 1'b0;
ce = 1'b0;
a = 0;
b = 0;
rst = 1'b1;
repeat (10) begin
#10;
clk = 1'b1;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
#10;
clk = 1'b0;
end
rst = 1'b0;
repeat (10000) begin
clkcycle;
ce = 1; //$urandom & $urandom;
//rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
a = $urandom & ~(1 << (SIZEIN-1));
b = $urandom & ~(1 << (SIZEIN-1));
end
if (errcount == 0) begin
$display("All tests passed.");
$finish;
end else begin
$display("Caught %1d errors.", errcount);
$stop;
end
end
macc2 ref (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(REF_accum_out),
.overflow(REF_overflow)
);
macc2_uut uut (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(accum_out),
.overflow(overflow)
);
endmodule

7
tests/arch/analogdevices/mul_unsigned.ys
View file

@ -5,7 +5,6 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG select -assert-count 1 t:RBBDSP
select -assert-count 1 t:DSP48E1 select -assert-count 75 t:FFRE
select -assert-count 30 t:FFRE select -assert-none t:RBBDSP t:FFRE %% t:* %D
select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D

4
tests/arch/analogdevices/mux.ys
View file

@ -44,7 +44,7 @@ select -assert-max 2 t:LUT3
select -assert-max 2 t:LUT4 select -assert-max 2 t:LUT4
select -assert-min 4 t:LUT6 select -assert-min 4 t:LUT6
select -assert-max 7 t:LUT6 select -assert-max 7 t:LUT6
select -assert-max 2 t:MUXF7 select -assert-max 2 t:LUTMUX7
dump dump
select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D select -assert-none t:LUT6 t:LUT4 t:LUT3 t:LUTMUX7 %% t:* %D

3
tests/arch/analogdevices/shifter.ys
View file

@ -6,6 +6,5 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 8 t:FFRE select -assert-count 8 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D select -assert-none t:FFRE %% t:* %D

13
tests/arch/analogdevices/tribuf.ys
View file

@ -1,13 +0,0 @@
read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/analogdevices/cells_sim.v -map +/simcells.v synth_analogdevices # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 2 t:INBUF
select -assert-count 1 t:INV
select -assert-count 1 t:OBUFT
select -assert-none t:INBUF t:INV t:OBUFT %% t:* %D