From b136a3c41724ab531172a272968e63634c39a9d6 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 10 Nov 2025 13:19:12 +0000 Subject: [PATCH] synth_analogdevices: update timing model and tests --- techlibs/analogdevices/cells_sim.v | 271 ++++++++++-------- tests/arch/analogdevices/abc9_dff.ys | 142 --------- tests/arch/analogdevices/add_sub.ys | 4 +- tests/arch/analogdevices/adffs.ys | 16 +- tests/arch/analogdevices/asym_ram_sdp.ys | 16 +- .../analogdevices/asym_ram_sdp_read_wider.v | 1 + .../analogdevices/asym_ram_sdp_write_wider.v | 1 + tests/arch/analogdevices/attributes_test.ys | 12 +- tests/arch/analogdevices/blockram.ys | 26 +- tests/arch/analogdevices/bug1460.ys | 4 +- tests/arch/analogdevices/bug1605.ys | 19 -- tests/arch/analogdevices/bug3670.v | 13 - tests/arch/analogdevices/bug3670.ys | 3 - tests/arch/analogdevices/counter.ys | 6 +- tests/arch/analogdevices/dffs.ys | 12 +- tests/arch/analogdevices/dsp_abc9.ys | 22 +- tests/arch/analogdevices/fsm.ys | 5 +- tests/arch/analogdevices/logic.ys | 4 +- tests/arch/analogdevices/lutram.ys | 8 +- tests/arch/analogdevices/macc.sh | 6 - tests/arch/analogdevices/macc.v | 84 ------ tests/arch/analogdevices/macc.ys | 32 --- tests/arch/analogdevices/macc_tb.v | 96 ------- tests/arch/analogdevices/mul_unsigned.ys | 7 +- tests/arch/analogdevices/mux.ys | 4 +- tests/arch/analogdevices/shifter.ys | 3 +- tests/arch/analogdevices/tribuf.ys | 13 - 27 files changed, 213 insertions(+), 617 deletions(-) delete mode 100644 tests/arch/analogdevices/abc9_dff.ys delete mode 100644 tests/arch/analogdevices/bug1605.ys delete mode 100644 tests/arch/analogdevices/bug3670.v delete mode 100644 tests/arch/analogdevices/bug3670.ys delete mode 100644 tests/arch/analogdevices/macc.sh delete mode 100644 tests/arch/analogdevices/macc.v delete mode 100644 tests/arch/analogdevices/macc.ys delete mode 100644 tests/arch/analogdevices/macc_tb.v delete mode 100644 tests/arch/analogdevices/tribuf.ys diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 402c421fa..505a2e07a 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -471,15 +471,15 @@ module FFRE ( input R ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); $setup(R , posedge C, 128); - if (R) (posedge C => (Q : 1'b0)) = 280; - if (!R && CE) (posedge C => (Q : D)) = 280; + if (R) (posedge C => (Q : 1'b0)) = 224; + if (!R && CE) (posedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP @@ -487,10 +487,8 @@ module FFRE ( $setup(D , posedge C, 119); $setup(CE, posedge C, 385); $setup(R , posedge C, 565); - // HACK: no clock-to-Q timings; using FFCE timing - if (R) (posedge C => (Q : 1'b0)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!R && CE) (posedge C => (Q : D)) = 689; + if (R) (posedge C => (Q : 1'b0)) = 672; + if (!R && CE) (posedge C => (Q : D)) = 672; endspecify `endif endmodule @@ -505,15 +503,15 @@ module FFRE_N ( input R ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); $setup(R , negedge C, 128); - if (R) (negedge C => (Q : 1'b0)) = 280; - if (!R && CE) (negedge C => (Q : D)) = 280; + if (R) (negedge C => (Q : 1'b0)) = 224; + if (!R && CE) (negedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP @@ -521,14 +519,13 @@ module FFRE_N ( $setup(D , negedge C, 119); $setup(CE, negedge C, 385); $setup(R , negedge C, 565); - // HACK: no clock-to-Q timings; using FFCE timing - if (R) (negedge C => (Q : 1'b0)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!R && CE) (negedge C => (Q : D)) = 689; + if (R) (negedge C => (Q : 1'b0)) = 672; + if (!R && CE) (negedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_flop, lib_whitebox *) module FFSE ( output reg Q, (* clkbuf_sink *) @@ -538,30 +535,29 @@ module FFSE ( input S ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); $setup(S , posedge C, 128); - if (S) (negedge C => (Q : 1'b1)) = 280; - if (!S && CE) (posedge C => (Q : D)) = 280; + if (S) (posedge C => (Q : 1'b1)) = 224; + if (!S && CE) (posedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP specify $setup(D , posedge C, 119); $setup(CE, posedge C, 385); - $setup(S , posedge C, 584); - // HACK: no clock-to-Q timings; using FFCE timing - if (S) (negedge C => (Q : 1'b1)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!S && CE) (posedge C => (Q : D)) = 689; + $setup(S , posedge C, 565); + if (S) (posedge C => (Q : 1'b1)) = 672; + if (!S && CE) (posedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_flop, lib_whitebox *) module FFSE_N ( output reg Q, (* clkbuf_sink *) @@ -571,30 +567,29 @@ module FFSE_N ( input S ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , negedge C, 31); $setup(CE, negedge C, 122); $setup(S , negedge C, 128); - if (S) (negedge C => (Q : 1'b1)) = 280; - if (!S && CE) (negedge C => (Q : D)) = 280; + if (S) (negedge C => (Q : 1'b1)) = 224; + if (!S && CE) (negedge C => (Q : D)) = 224; endspecify `endif `ifdef IS_T40LP specify $setup(D , negedge C, 119); $setup(CE, negedge C, 385); - $setup(S , negedge C, 584); - // HACK: no clock-to-Q timings; using FFCE timing - if (S) (negedge C => (Q : 1'b1)) = 689; - // HACK: no clock-to-Q timings; using FFCE timing - if (!S && CE) (negedge C => (Q : D)) = 689; + $setup(S , negedge C, 565); + if (S) (negedge C => (Q : 1'b1)) = 672; + if (!S && CE) (negedge C => (Q : D)) = 672; endspecify `endif endmodule +(* abc9_box, lib_whitebox *) module FFCE ( output reg Q, (* clkbuf_sink *) @@ -604,24 +599,33 @@ module FFCE ( input D ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify $setup(D , posedge C, 31); $setup(CE, posedge C, 122); + $setup(CLR, posedge C, 0 /* missing? */); if (!CLR && CE) (posedge C => (Q : D)) = 280; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify $setup(D , posedge C, 119); $setup(CE, posedge C, 385); + $setup(CLR, posedge C, 0 /* missing? */); if (!CLR && CE) (posedge C => (Q : D)) = 689; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule +(* abc9_box, lib_whitebox *) module FFCE_N ( output reg Q, (* clkbuf_sink *) @@ -631,20 +635,28 @@ module FFCE_N ( input D ); parameter [0:0] INIT = 1'b0; - initial Q <= INIT; + initial Q = INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE, negedge C, 122); + $setup(D, negedge C, 31); + $setup(CE, negedge C, 122); + $setup(CLR, negedge C, 0 /* missing? */); if (!CLR && CE) (negedge C => (Q : D)) = 280; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify - $setup(D , negedge C, 119); - $setup(CE, negedge C, 385); + $setup(D, negedge C, 119); + $setup(CE, negedge C, 385); + $setup(CLR, negedge C, 0 /* missing? */); if (!CLR && CE) (negedge C => (Q : D)) = 689; +`ifdef YOSYS + if (CLR) (CLR => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule @@ -658,21 +670,28 @@ module FFPE ( input D ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , posedge C, 31); - $setup(CE, posedge C, 122); - if (!PRE && CE) (posedge C => (Q : D)) = 291; + $setup(D, posedge C, 31); + $setup(CE, posedge C, 122); + $setup(PRE, posedge C, 0 /* missing? */); + if (!PRE && CE) (posedge C => (Q : D)) = 224; +`ifdef YOSYS + if (PRE) (PRE => Q) = 0 /* missing? */; +`endif endspecify `endif `ifdef IS_T40LP specify - $setup(D , posedge C, 119); - $setup(CE, posedge C, 385); - // HACK: no clock-to-Q timings; using FFPE_N timing - if (!PRE && CE) (posedge C => (Q : D)) = 712; + $setup(D, posedge C, 119); + $setup(CE, posedge C, 385); + $setup(PRE, posedge C, 0 /* missing? */); + if (!PRE && CE) (posedge C => (Q : D)) = 672; +`ifdef YOSYS + if (PRE) (PRE => Q) = 0 /* missing? */; +`endif endspecify `endif endmodule @@ -686,22 +705,28 @@ module FFPE_N ( input D ); parameter [0:0] INIT = 1'b1; - initial Q <= INIT; + initial Q = INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; `ifdef IS_T16FFC specify - $setup(D , negedge C, 31); - $setup(CE , negedge C, 122); + $setup(D, negedge C, 28); + $setup(CE, negedge C, 28); + $setup(PRE, negedge C, 28); if (!PRE && CE) (negedge C => (Q : D)) = 291; +`ifdef YOSYS + if (PRE) (PRE => Q) = 57; +`endif endspecify `endif `ifdef IS_T40LP specify - // HACK: no D setup time; using FFPE timing - $setup(D , negedge C, 119); - // HACK: no CE setup time; using FFPE timing - $setup(CE, negedge C, 385); + $setup(D, negedge C, 84); + $setup(CE, negedge C, 84); + $setup(PRE, negedge C, 84); if (!PRE && CE) (negedge C => (Q : D)) = 712; +`ifdef YOSYS + if (PRE) (PRE => Q) = 57; +`endif endspecify `endif endmodule @@ -726,14 +751,13 @@ module RAMS32X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => O) = 63; (A1 => O) = 63; (A2 => O) = 63; @@ -744,14 +768,13 @@ module RAMS32X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => O) = 168; (A1 => O) = 168; (A2 => O) = 168; @@ -778,15 +801,14 @@ module RAMS64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(A5, posedge WCLK, 28); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => O) = 161; (A1 => O) = 161; (A2 => O) = 161; @@ -798,15 +820,14 @@ module RAMS64X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(A5, posedge WCLK, 84); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => O) = 466; (A1 => O) = 466; (A2 => O) = 466; @@ -832,26 +853,26 @@ module RAMD32X1 ( ); parameter INIT = 32'h0; wire [4:0] a = {A4, A3, A2, A1, A0}; - wire [4:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; reg [31:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); // HACK: No timing arcs for SPO; using ones for DPO // (are we meant to use the single-port timings here?) (A0 => SPO) = 66; @@ -870,19 +891,19 @@ module RAMD32X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); // HACK: No timing arcs for SPO; using ones for DPO // (are we meant to use the single-port timings here?) (A0 => SPO) = 142; @@ -920,21 +941,21 @@ module RAMD64X1 ( always @(posedge WCLK) if (WE) mem[a] <= D; `ifdef IS_T16FFC specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 28); + $setup(A1, posedge WCLK, 28); + $setup(A2, posedge WCLK, 28); + $setup(A3, posedge WCLK, 28); + $setup(A4, posedge WCLK, 28); + $setup(A5, posedge WCLK, 28); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 28); + $setup(WE, posedge WCLK, 28); (A0 => SPO) = 161; (A1 => SPO) = 161; (A2 => SPO) = 161; @@ -953,21 +974,21 @@ module RAMD64X1 ( `endif `ifdef IS_T40LP specify - // HACK: no setup timing - $setup(A0, posedge WCLK, 0); - $setup(A1, posedge WCLK, 0); - $setup(A2, posedge WCLK, 0); - $setup(A3, posedge WCLK, 0); - $setup(A4, posedge WCLK, 0); - $setup(A5, posedge WCLK, 0); + // HACK: partial setup timing + $setup(A0, posedge WCLK, 84); + $setup(A1, posedge WCLK, 84); + $setup(A2, posedge WCLK, 84); + $setup(A3, posedge WCLK, 84); + $setup(A4, posedge WCLK, 84); + $setup(A5, posedge WCLK, 84); $setup(DPRA0, posedge WCLK, 0); $setup(DPRA1, posedge WCLK, 0); $setup(DPRA2, posedge WCLK, 0); $setup(DPRA3, posedge WCLK, 0); $setup(DPRA4, posedge WCLK, 0); $setup(DPRA5, posedge WCLK, 0); - $setup(D, posedge WCLK, 0); - $setup(WE, posedge WCLK, 0); + $setup(D, posedge WCLK, 84); + $setup(WE, posedge WCLK, 84); (A0 => SPO) = 466; (A1 => SPO) = 466; (A2 => SPO) = 466; @@ -1091,7 +1112,7 @@ parameter FF_SYNC_RST = 1'b0; specify if (!REG_A) (A *> P) = 1000; if (!REG_B) (B *> P) = 1000; - if (!REG_D[0]) (D *> P) = 1000; + if (!REG_D) (D *> P) = 1000; endspecify // Much of this functionality is TODO. @@ -1112,7 +1133,7 @@ module RBRAM #( parameter DATA_WIDTH = 40, parameter ADDR_WIDTH = 12, parameter WE_WIDTH = 20, - parameter PERR_WIDTH = 4, + parameter PERR_WIDTH = 4 ) ( output [DATA_WIDTH-1:0] QA, input [DATA_WIDTH-1:0] DA, @@ -1137,7 +1158,7 @@ module RBRAM #( output MBEA, output MBEB, input SLP, - input PD, + input PD ); endmodule @@ -1152,7 +1173,7 @@ module RBRAM2 #( parameter DATA_WIDTH = 40, parameter ADDR_WIDTH = 13, parameter WE_WIDTH = 20, - parameter PERR_WIDTH = 4, + parameter PERR_WIDTH = 4 ) ( output [DATA_WIDTH-1:0] QA, input [DATA_WIDTH-1:0] DA, @@ -1177,7 +1198,7 @@ module RBRAM2 #( output MBEA, output MBEB, input SLP, - input PD, + input PD ); endmodule diff --git a/tests/arch/analogdevices/abc9_dff.ys b/tests/arch/analogdevices/abc9_dff.ys deleted file mode 100644 index 891330726..000000000 --- a/tests/arch/analogdevices/abc9_dff.ys +++ /dev/null @@ -1,142 +0,0 @@ -logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*" -logger -nowarn "Ignoring boxed module .*\." - -read_verilog < RAMB18E1 +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2 # w4b | r16b design -reset read_verilog asym_ram_sdp_read_wider.v synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w8b | r16b design -reset read_verilog asym_ram_sdp_read_wider.v chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w4b | r32b design -reset read_verilog asym_ram_sdp_read_wider.v chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 2 t:RBRAM2 # w16b | r4b design -reset read_verilog asym_ram_sdp_write_wider.v synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w16b | r8b design -reset read_verilog asym_ram_sdp_write_wider.v chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w32b | r4b design -reset read_verilog asym_ram_sdp_write_wider.v chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_write_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # w4b | r24b design -reset @@ -46,5 +46,5 @@ read_verilog asym_ram_sdp_read_wider.v chparam -set SIZEA 768 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider synth_analogdevices -top asym_ram_sdp_read_wider -noiopad -select -assert-count 1 t:RAMB18E1 +select -assert-count 2 t:RBRAM2 diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v index 8743209e3..183b0cf4f 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -46,6 +46,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, localparam RATIO = maxWIDTH / minWIDTH; localparam log2RATIO = log2(RATIO); + (* ram_style="block" *) reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [WIDTHB-1:0] readB; diff --git a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v index cd61a3ccc..df817894f 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_write_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_write_wider.v @@ -46,6 +46,7 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, localparam RATIO = maxWIDTH / minWIDTH; localparam log2RATIO = log2(RATIO); + (* ram_style="block" *) reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; reg [WIDTHB-1:0] readB; diff --git a/tests/arch/analogdevices/attributes_test.ys b/tests/arch/analogdevices/attributes_test.ys index 8d55d96fd..03d6decff 100644 --- a/tests/arch/analogdevices/attributes_test.ys +++ b/tests/arch/analogdevices/attributes_test.ys @@ -3,7 +3,7 @@ read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 +# select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive. # Check that distributed memory without parameters is not modified design -reset @@ -11,7 +11,8 @@ read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram synth_analogdevices -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAM32M +select -assert-count 8 t:RAMS64X1 +select -assert-count 8 t:FFRE # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset @@ -19,7 +20,8 @@ read_verilog ../common/memory_attributes/attributes_test.v setattr -set ram_style "distributed" block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 64 t:RAM64X1S +select -assert-count 64 t:RAMS64X1 +select -assert-count 4 t:FFRE # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset @@ -27,11 +29,11 @@ read_verilog ../common/memory_attributes/attributes_test.v setattr -set logic_block 1 block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module -select -assert-count 0 t:RAMB18E1 +select -assert-count 0 t:RBRAM2 # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v synth_analogdevices -top distributed_ram_manual -noiopad cd distributed_ram_manual # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 +# select -assert-count 1 t:RBRAM2 # This gets implemented in logic instead diff --git a/tests/arch/analogdevices/blockram.ys b/tests/arch/analogdevices/blockram.ys index 26d5634ba..f6efa5ba8 100644 --- a/tests/arch/analogdevices/blockram.ys +++ b/tests/arch/analogdevices/blockram.ys @@ -1,32 +1,35 @@ ### TODO: Not running equivalence checking because BRAM models does not exists ### currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RBRAM2 read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +setattr -set ram_style "block" sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 # Anything memory bits < 1024 -> LUTRAM design -reset @@ -34,8 +37,9 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM64M +select -assert-count 0 t:RBRAM2 +select -assert-count 8 t:RAMD64X1 +select -assert-count 2 t:FFRE # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset @@ -43,7 +47,7 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 +select -assert-count 1 t:RBRAM2 ### With parameters @@ -54,7 +58,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v @@ -62,7 +66,7 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 +select -assert-count 0 t:RBRAM2 design -reset read_verilog ../common/blockram.v @@ -70,4 +74,4 @@ hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 +select -assert-count 1 t:RBRAM2 diff --git a/tests/arch/analogdevices/bug1460.ys b/tests/arch/analogdevices/bug1460.ys index d00292c19..66fb96a5b 100644 --- a/tests/arch/analogdevices/bug1460.ys +++ b/tests/arch/analogdevices/bug1460.ys @@ -30,5 +30,5 @@ EOT synth_analogdevices -noiopad cd register_file -select -assert-count 33 t:RAM32M -select -assert-none t:* t:BUFG %d t:RAM32M %d +select -assert-count 192 t:RAMD32X1 +select -assert-none t:RAMD32X1 %% t:* %D diff --git a/tests/arch/analogdevices/bug1605.ys b/tests/arch/analogdevices/bug1605.ys deleted file mode 100644 index d3d793718..000000000 --- a/tests/arch/analogdevices/bug1605.ys +++ /dev/null @@ -1,19 +0,0 @@ -read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; - -// Output accumulation result -assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; - -endmodule diff --git a/tests/arch/analogdevices/macc.ys b/tests/arch/analogdevices/macc.ys deleted file mode 100644 index 79b330016..000000000 --- a/tests/arch/analogdevices/macc.ys +++ /dev/null @@ -1,32 +0,0 @@ -read_verilog macc.v -design -save read - -hierarchy -top macc -proc -#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO -equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:FFRE -select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FFRE t:DSP48E1 %% t:* %D - -design -load read -hierarchy -top macc2 -proc -#equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad ### TODO -equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc2 # Constrain all select calls below inside the top module - -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 1 t:FFRE -select -assert-count 1 t:LUT2 -select -assert-count 40 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FFRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/analogdevices/macc_tb.v b/tests/arch/analogdevices/macc_tb.v deleted file mode 100644 index 64aed05c4..000000000 --- a/tests/arch/analogdevices/macc_tb.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps - -module testbench; - - parameter SIZEIN = 16, SIZEOUT = 40; - reg clk, ce, rst; - reg signed [SIZEIN-1:0] a, b; - output signed [SIZEOUT-1:0] REF_accum_out, accum_out; - output REF_overflow, overflow; - - integer errcount = 0; - - reg ERROR_FLAG = 0; - - task clkcycle; - begin - #5; - clk = ~clk; - #10; - clk = ~clk; - #2; - ERROR_FLAG = 0; - if (REF_accum_out !== accum_out) begin - $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - if (REF_overflow !== overflow) begin - $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - #3; - end - endtask - - initial begin - //$dumpfile("test_macc.vcd"); - //$dumpvars(0, testbench); - - #2; - clk = 1'b0; - ce = 1'b0; - a = 0; - b = 0; - - rst = 1'b1; - repeat (10) begin - #10; - clk = 1'b1; - #10; - clk = 1'b0; - #10; - clk = 1'b1; - #10; - clk = 1'b0; - end - rst = 1'b0; - - repeat (10000) begin - clkcycle; - ce = 1; //$urandom & $urandom; - //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; - a = $urandom & ~(1 << (SIZEIN-1)); - b = $urandom & ~(1 << (SIZEIN-1)); - end - - if (errcount == 0) begin - $display("All tests passed."); - $finish; - end else begin - $display("Caught %1d errors.", errcount); - $stop; - end - end - - macc2 ref ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(REF_accum_out), - .overflow(REF_overflow) - ); - - macc2_uut uut ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(accum_out), - .overflow(overflow) - ); -endmodule diff --git a/tests/arch/analogdevices/mul_unsigned.ys b/tests/arch/analogdevices/mul_unsigned.ys index 99a0a3f0d..5bdbdaac4 100644 --- a/tests/arch/analogdevices/mul_unsigned.ys +++ b/tests/arch/analogdevices/mul_unsigned.ys @@ -5,7 +5,6 @@ proc equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 30 t:FFRE -select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D +select -assert-count 1 t:RBBDSP +select -assert-count 75 t:FFRE +select -assert-none t:RBBDSP t:FFRE %% t:* %D diff --git a/tests/arch/analogdevices/mux.ys b/tests/arch/analogdevices/mux.ys index 579519ce5..375ce90f2 100644 --- a/tests/arch/analogdevices/mux.ys +++ b/tests/arch/analogdevices/mux.ys @@ -44,7 +44,7 @@ select -assert-max 2 t:LUT3 select -assert-max 2 t:LUT4 select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 -select -assert-max 2 t:MUXF7 +select -assert-max 2 t:LUTMUX7 dump -select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:LUTMUX7 %% t:* %D diff --git a/tests/arch/analogdevices/shifter.ys b/tests/arch/analogdevices/shifter.ys index 6eab4bee5..3cd67cb93 100644 --- a/tests/arch/analogdevices/shifter.ys +++ b/tests/arch/analogdevices/shifter.ys @@ -6,6 +6,5 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG select -assert-count 8 t:FFRE -select -assert-none t:BUFG t:FFRE %% t:* %D +select -assert-none t:FFRE %% t:* %D diff --git a/tests/arch/analogdevices/tribuf.ys b/tests/arch/analogdevices/tribuf.ys deleted file mode 100644 index 0be9f8d6f..000000000 --- a/tests/arch/analogdevices/tribuf.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog ../common/tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/analogdevices/cells_sim.v -map +/simcells.v synth_analogdevices # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 2 t:INBUF -select -assert-count 1 t:INV -select -assert-count 1 t:OBUFT -select -assert-none t:INBUF t:INV t:OBUFT %% t:* %D