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synth_analogdevices: update timing model and tests

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This commit is contained in:
Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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7
tests/arch/analogdevices/mul_unsigned.ys
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@ -5,7 +5,6 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 30 t:FFRE
select -assert-none t:DSP48E1 t:FFRE t:BUFG %% t:* %D
select -assert-count 1 t:RBBDSP
select -assert-count 75 t:FFRE
select -assert-none t:RBBDSP t:FFRE %% t:* %D