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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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8
tests/arch/analogdevices/lutram.ys
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@ -13,8 +13,8 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
design -load postopt
cd lutram_1w1r
select -assert-count 8 t:FFRE
select -assert-count 8 t:RAMS32X1
select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
select -assert-count 8 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
design -reset
@ -90,8 +90,8 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
design -load postopt
cd lutram_1w1r
select -assert-count 6 t:FFRE
select -assert-count 6 t:RAMS32X1
select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
select -assert-count 6 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
design -reset