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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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12
tests/arch/analogdevices/dffs.ys
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@ -6,9 +6,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D
select -assert-none t:FFRE %% t:* %D
design -load read
@ -17,9 +16,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D
select -assert-none t:FFRE %% t:* %D
design -load read
@ -28,9 +26,8 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D
select -assert-none t:FFRE %% t:* %D
design -load read
@ -39,7 +36,6 @@ proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -dff -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-none t:BUFG t:FFRE %% t:* %D
select -assert-none t:FFRE %% t:* %D