mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-27 07:49:50 +00:00
Code Activity

synth_analogdevices: update timing model and tests

Browse source
This commit is contained in:
Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
Download patch file Download diff file Expand all files Collapse all files

16
tests/arch/analogdevices/adffs.ys
View file

@ -6,10 +6,9 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFCE
select -assert-none t:BUFG t:FFCE %% t:* %D
select -assert-none t:FFCE %% t:* %D
design -load read
@ -18,11 +17,10 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFCE
select -assert-count 1 t:INV
select -assert-count 1 t:LUT1
select -assert-none t:BUFG t:FFCE t:INV %% t:* %D
select -assert-none t:FFCE t:LUT1 %% t:* %D
design -load read
@ -31,11 +29,10 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE
select -assert-count 1 t:LUT2
stat
select -assert-none t:BUFG t:FFRE t:LUT2 %% t:* %D
select -assert-none t:FFRE t:LUT2 %% t:* %D
design -load read
@ -44,8 +41,7 @@ proc
equiv_opt -async2sync -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FFRE_N
select -assert-count 1 t:INV
select -assert-count 1 t:LUT1
select -assert-none t:BUFG t:FFRE_N t:INV %% t:* %D
select -assert-none t:FFRE_N t:LUT1 %% t:* %D