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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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4
tests/arch/analogdevices/add_sub.ys
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@ -9,5 +9,5 @@ cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:LUT2
select -assert-count 2 t:CRY4
select -assert-none t:LUT2 t:CRY4 %% t:* %D
select -assert-count 2 t:CRY4INIT
select -assert-none t:LUT2 t:CRY4 t:CRY4INIT %% t:* %D