Moving images and static folders

Images now included relative to the `docs/source` folder instead of the rst file.
Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs).

docs/source/yosys_internals/flow/control_and_data.rst

@@ -9,7 +9,7 @@ a predetermined order, each consuming the data generated by the last subsystem
 and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
-.. figure:: ../../../images/approach_flow.*
+.. figure:: /_images/approach_flow.*
 	:class: width-helper
 	:name: fig:approach_flow
 

docs/source/yosys_internals/flow/overview.rst

@@ -40,7 +40,7 @@ possible it is key that (1) all passes operate on the same data structure
 (RTLIL) and (2) that this data structure is powerful enough to represent the
 design in different stages of the synthesis.
 
-.. figure:: ../../../images/overview_flow.*
+.. figure:: /_images/overview_flow.*
 	:class: width-helper
 	:name: fig:Overview_flow
 

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation
 is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
-.. figure:: ../../../images/verilog_flow.*
+.. figure:: /_images/verilog_flow.*
 	:class: width-helper
 	:name: fig:Verilog_flow