From b0f8059bceeb96362c588c05cf714439d3ac38f9 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 10 Oct 2023 10:12:50 +1300 Subject: [PATCH] Moving images and static folders Images now included relative to the `docs/source` folder instead of the rst file. Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs). --- docs/.gitignore | 18 ++-- .../_images}/011/example_out.tex | 0 .../_images}/011/select_prod.tex | 0 .../_images}/011/splitnets_libfile.tex | 0 .../_images}/011/submod_dots.tex | 0 docs/{images => source/_images}/Makefile | 0 .../_images}/approach_flow.png | Bin .../_images}/approach_flow.tex | 0 .../_images}/basics_abstractions.png | Bin .../_images}/basics_abstractions.tex | 0 .../{images => source/_images}/basics_ast.png | Bin .../{images => source/_images}/basics_ast.tex | 0 .../_images}/basics_flow.png | Bin .../_images}/basics_flow.tex | 0 .../_images}/basics_parsetree.png | Bin .../_images}/basics_parsetree.tex | 0 .../_images}/levels_of_abstraction.tex | 0 .../_images}/overview_flow.png | Bin .../_images}/overview_flow.tex | 0 .../_images}/overview_rtlil.png | Bin .../_images}/overview_rtlil.tex | 0 .../_images}/simplified_rtlil.tex | 0 .../_images}/verilog_flow.png | Bin .../_images}/verilog_flow.tex | 0 docs/source/_static/custom.css | 15 ++++ docs/{static => source/_static}/favico.png | Bin docs/{static => source/_static}/logo.png | Bin docs/source/_static/yosyshq.css | 26 ++++++ .../APPNOTE_011_Design_Investigation.rst | 20 ++--- docs/source/appendix/primer.rst | 8 +- docs/source/conf.py | 6 +- docs/source/getting_started/examples.rst | 8 +- .../source/getting_started/typical_phases.rst | 22 ++--- docs/source/introduction.rst | 2 +- .../using_yosys/more_scripting/selections.rst | 6 +- docs/source/using_yosys/yosys_flows.rst | 40 ++++----- docs/source/yosys_internals/extensions.rst | 2 +- .../yosys_internals/flow/control_and_data.rst | 2 +- docs/source/yosys_internals/flow/overview.rst | 2 +- .../yosys_internals/flow/verilog_frontend.rst | 2 +- .../yosys_internals/formats/rtlil_rep.rst | 2 +- docs/source/yosys_internals/techmap.rst | 10 +-- docs/static/custom.css | 1 - docs/static/yosyshq.css | 78 ------------------ 44 files changed, 116 insertions(+), 154 deletions(-) rename docs/{images => source/_images}/011/example_out.tex (100%) rename docs/{images => source/_images}/011/select_prod.tex (100%) rename docs/{images => source/_images}/011/splitnets_libfile.tex (100%) rename docs/{images => source/_images}/011/submod_dots.tex (100%) rename docs/{images => source/_images}/Makefile (100%) rename docs/{images => source/_images}/approach_flow.png (100%) rename docs/{images => source/_images}/approach_flow.tex (100%) rename docs/{images => source/_images}/basics_abstractions.png (100%) rename docs/{images => source/_images}/basics_abstractions.tex (100%) rename docs/{images => source/_images}/basics_ast.png (100%) rename docs/{images => source/_images}/basics_ast.tex (100%) rename docs/{images => source/_images}/basics_flow.png (100%) rename docs/{images => source/_images}/basics_flow.tex (100%) rename docs/{images => source/_images}/basics_parsetree.png (100%) rename docs/{images => source/_images}/basics_parsetree.tex (100%) rename docs/{images => source/_images}/levels_of_abstraction.tex (100%) rename docs/{images => source/_images}/overview_flow.png (100%) rename docs/{images => source/_images}/overview_flow.tex (100%) rename docs/{images => source/_images}/overview_rtlil.png (100%) rename docs/{images => source/_images}/overview_rtlil.tex (100%) rename docs/{images => source/_images}/simplified_rtlil.tex (100%) rename docs/{images => source/_images}/verilog_flow.png (100%) rename docs/{images => source/_images}/verilog_flow.tex (100%) create mode 100644 docs/source/_static/custom.css rename docs/{static => source/_static}/favico.png (100%) rename docs/{static => source/_static}/logo.png (100%) create mode 100644 docs/source/_static/yosyshq.css delete mode 100644 docs/static/custom.css delete mode 100644 docs/static/yosyshq.css diff --git a/docs/.gitignore b/docs/.gitignore index 40b781904..50f03d13c 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,12 +1,12 @@ /build/ /source/cmd /source/temp -/images/*.log -/images/*.aux -/images/*.pdf -/images/*.svg -/images/**/*.log -/images/**/*.aux -/images/**/*.pdf -/images/**/*.svg -/images/**/*.dot +/source/_images/*.log +/source/_images/*.aux +/source/_images/*.pdf +/source/_images/*.svg +/source/_images/**/*.log +/source/_images/**/*.aux +/source/_images/**/*.pdf +/source/_images/**/*.svg +/source/_images/**/*.dot diff --git a/docs/images/011/example_out.tex b/docs/source/_images/011/example_out.tex similarity index 100% rename from docs/images/011/example_out.tex rename to docs/source/_images/011/example_out.tex diff --git a/docs/images/011/select_prod.tex b/docs/source/_images/011/select_prod.tex similarity index 100% rename from docs/images/011/select_prod.tex rename to docs/source/_images/011/select_prod.tex diff --git a/docs/images/011/splitnets_libfile.tex b/docs/source/_images/011/splitnets_libfile.tex similarity index 100% rename from docs/images/011/splitnets_libfile.tex rename to docs/source/_images/011/splitnets_libfile.tex diff --git a/docs/images/011/submod_dots.tex b/docs/source/_images/011/submod_dots.tex similarity index 100% rename from docs/images/011/submod_dots.tex rename to docs/source/_images/011/submod_dots.tex diff --git a/docs/images/Makefile b/docs/source/_images/Makefile similarity index 100% rename from docs/images/Makefile rename to docs/source/_images/Makefile diff --git a/docs/images/approach_flow.png b/docs/source/_images/approach_flow.png similarity index 100% rename from docs/images/approach_flow.png rename to docs/source/_images/approach_flow.png diff --git a/docs/images/approach_flow.tex b/docs/source/_images/approach_flow.tex similarity index 100% rename from docs/images/approach_flow.tex rename to docs/source/_images/approach_flow.tex diff --git a/docs/images/basics_abstractions.png b/docs/source/_images/basics_abstractions.png similarity index 100% rename from docs/images/basics_abstractions.png rename to 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docs/images/verilog_flow.tex rename to docs/source/_images/verilog_flow.tex diff --git a/docs/source/_static/custom.css b/docs/source/_static/custom.css new file mode 100644 index 000000000..21ede09b4 --- /dev/null +++ b/docs/source/_static/custom.css @@ -0,0 +1,15 @@ +/* Reduce whitespace in cmd def pages */ +.cmd.def .highlight-yoscrypt, .cmd.def .highlight pre { + padding: 0%; + margin: 0%; +} + +.cmd.def .highlight-none, .cmd.def .highlight pre { + padding-top: 0%; + margin-top: 0%; +} + +/* Make images full width */ +.width-helper { + max-width: 100%; +} \ No newline at end of file diff --git a/docs/static/favico.png b/docs/source/_static/favico.png similarity index 100% rename from docs/static/favico.png rename to docs/source/_static/favico.png diff --git a/docs/static/logo.png b/docs/source/_static/logo.png similarity index 100% rename from docs/static/logo.png rename to docs/source/_static/logo.png diff --git a/docs/source/_static/yosyshq.css b/docs/source/_static/yosyshq.css new file mode 100644 index 000000000..57ae8f87a --- /dev/null +++ b/docs/source/_static/yosyshq.css @@ -0,0 +1,26 @@ +/* Don't hide the right sidebar as we're placing our fixed links there */ +aside.no-toc { + display: block !important; +} + +/* Colorful headings */ +h1 { + color: var(--color-brand-primary); + } + +h2, h3, h4, h5, h6 { + color: var(--color-brand-content); +} + +/* Use a different color for external links */ +a.external { + color: var(--color-brand-primary) !important; +} + +.wy-table-responsive table td { + white-space: normal; +} + +th { + text-align: left; +} diff --git a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst index 698f2da2c..5552408cc 100644 --- a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst +++ b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst @@ -60,7 +60,7 @@ Introduction to the show command y <= c ? a + b : 2'd0; endmodule -.. figure:: ../../images/011/example_out.* +.. figure:: /_images/011/example_out.* :class: width-helper :name: example_out @@ -134,7 +134,7 @@ leads us to the 3rd diagram in :numref:`example_out`. Here we see that the :cmd:ref:`proc`, but also determined correctly that it can remove the first ``$mux`` cell without changing the behavior of the circuit. -.. figure:: ../../images/011/splice.* +.. figure:: /_images/011/splice.* :class: width-helper :name: splice_dia @@ -144,7 +144,7 @@ leads us to the 3rd diagram in :numref:`example_out`. Here we see that the :caption: ``splice.v`` :name: splice_src -.. figure:: ../../images/011/splitnets_libfile.* +.. figure:: /_images/011/splitnets_libfile.* :class: width-helper :name: splitnets_libfile @@ -329,7 +329,7 @@ run from module-context and not design-context. Working with selections ----------------------- -.. figure:: ../../images/011/example_03.* +.. figure:: /_images/011/example_03.* :class: width-helper :name: seladd @@ -386,7 +386,7 @@ Operations on selections :name: sumprod :language: verilog -.. figure:: ../../images/011/sumprod_00.* +.. figure:: /_images/011/sumprod_00.* :class: width-helper :name: sumprod_00 @@ -434,7 +434,7 @@ be achieved using the ``%x`` action, that broadens the selection, i.e. for each selected wire it selects all cells connected to the wire and vice versa. So ``show a:sumstuff %x`` yields the diagram shown in :numref:`sumprod_01`. -.. figure:: ../../images/011/sumprod_01.* +.. figure:: /_images/011/sumprod_01.* :class: width-helper :name: sumprod_01 @@ -471,7 +471,7 @@ performing the ``%ci`` action three times. The action ``%ci*`` performs the ``%ci`` action over and over again until it has no effect anymore. -.. figure:: ../../images/011/select_prod.* +.. figure:: /_images/011/select_prod.* :class: width-helper :name: select_prod @@ -493,7 +493,7 @@ see the diagram shown in :numref:`memdemo_00`. :name: memdemo_src :language: verilog -.. figure:: ../../images/011/memdemo_00.* +.. figure:: /_images/011/memdemo_00.* :class: width-helper :name: memdemo_00 @@ -538,7 +538,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input: show y %ci2:-[CLK] -.. figure:: ../../images/011/memdemo_01.* +.. figure:: /_images/011/memdemo_01.* :class: width-helper :name: memdemo_01 @@ -616,7 +616,7 @@ the circuit from :numref:`memdemo_src` and :numref:`memdemo_00` into its components. The ``-name`` option is used to specify the name of the new module and also the name of the new cell in the current module. -.. figure:: ../../images/011/submod_dots.* +.. figure:: /_images/011/submod_dots.* :class: width-helper :name: submod_dots diff --git a/docs/source/appendix/primer.rst b/docs/source/appendix/primer.rst index 6c9aa1673..9a905c6f2 100644 --- a/docs/source/appendix/primer.rst +++ b/docs/source/appendix/primer.rst @@ -23,7 +23,7 @@ circuit to a functionally equivalent low-level representation of a circuit. :numref:`Figure %s ` lists the different levels of abstraction and how they relate to different kinds of synthesis. -.. figure:: ../../images/basics_abstractions.* +.. figure:: /_images/basics_abstractions.* :class: width-helper :name: fig:Basics_abstractions @@ -498,7 +498,7 @@ Then the synthesizable description is transformed to lower-level representations using a series of tools and the results are again verified using simulation. This process is illustrated in :numref:`Fig. %s `. -.. figure:: ../../images/basics_flow.* +.. figure:: /_images/basics_flow.* :class: width-helper :name: fig:Basics_flow @@ -597,7 +597,7 @@ Let's consider the following BNF (in Bison syntax): assign_stmt: TOK_ASSIGN TOK_IDENTIFIER TOK_EQ expr TOK_SEMICOLON; expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr; -.. figure:: ../../images/basics_parsetree.* +.. figure:: /_images/basics_parsetree.* :class: width-helper :name: fig:Basics_parsetree @@ -626,7 +626,7 @@ Usually the AST is then converted into yet another representation that is more suitable for further processing. In compilers this is often an assembler-like three-address-code intermediate representation. :cite:p:`Dragonbook` -.. figure:: ../../images/basics_ast.* +.. figure:: /_images/basics_ast.* :class: width-helper :name: fig:Basics_ast diff --git a/docs/source/conf.py b/docs/source/conf.py index a043f0b49..003887498 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -9,8 +9,8 @@ copyright ='2022 YosysHQ GmbH' # select HTML theme html_theme = 'furo' templates_path = ["_templates"] -html_logo = '../static/logo.png' -html_favicon = '../static/favico.png' +html_logo = '_static/logo.png' +html_favicon = '_static/favico.png' html_css_files = ['yosyshq.css', 'custom.css'] html_theme_options = { @@ -34,7 +34,7 @@ html_theme_options = { } # These folders are copied to the documentation's HTML output -html_static_path = ['../static', "../images"] +html_static_path = ['_static', "_images"] # code blocks style pygments_style = 'colorful' diff --git a/docs/source/getting_started/examples.rst b/docs/source/getting_started/examples.rst index 0c3f66365..8342b685c 100644 --- a/docs/source/getting_started/examples.rst +++ b/docs/source/getting_started/examples.rst @@ -106,7 +106,7 @@ Step 1 Result: -.. figure:: ../../images/res/PRESENTATION_Intro/counter_00.* +.. figure:: /_images/res/PRESENTATION_Intro/counter_00.* :class: width-helper Step 2 @@ -118,7 +118,7 @@ Step 2 Result: -.. figure:: ../../images/res/PRESENTATION_Intro/counter_01.* +.. figure:: /_images/res/PRESENTATION_Intro/counter_01.* :class: width-helper Step 3 @@ -130,7 +130,7 @@ Step 3 Result: -.. figure:: ../../images/res/PRESENTATION_Intro/counter_02.* +.. figure:: /_images/res/PRESENTATION_Intro/counter_02.* :class: width-helper Step 4 @@ -142,5 +142,5 @@ Step 4 Result: -.. figure:: ../../images/res/PRESENTATION_Intro/counter_03.* +.. figure:: /_images/res/PRESENTATION_Intro/counter_03.* :class: width-helper diff --git a/docs/source/getting_started/typical_phases.rst b/docs/source/getting_started/typical_phases.rst index 9d48ac71b..a06ee1e17 100644 --- a/docs/source/getting_started/typical_phases.rst +++ b/docs/source/getting_started/typical_phases.rst @@ -94,10 +94,10 @@ Example :language: yoscrypt :caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.ys`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_01.* +.. figure:: /_images/res/PRESENTATION_ExSyn/proc_01.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_02.* +.. figure:: /_images/res/PRESENTATION_ExSyn/proc_02.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.v @@ -108,7 +108,7 @@ Example :language: yoscrypt :caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.ys`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_03.* +.. figure:: /_images/res/PRESENTATION_ExSyn/proc_03.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.ys @@ -150,7 +150,7 @@ The command :cmd:ref:`clean` can be used as alias for :cmd:ref:`opt_clean`. And Example ^^^^^^^ -.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_01.* +.. figure:: /_images/res/PRESENTATION_ExSyn/opt_01.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.ys @@ -161,7 +161,7 @@ Example :language: verilog :caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.v`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_02.* +.. figure:: /_images/res/PRESENTATION_ExSyn/opt_02.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.ys @@ -172,7 +172,7 @@ Example :language: verilog :caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.v`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_03.* +.. figure:: /_images/res/PRESENTATION_ExSyn/opt_03.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.ys @@ -183,7 +183,7 @@ Example :language: verilog :caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.v`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_04.* +.. figure:: /_images/res/PRESENTATION_ExSyn/opt_04.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.v @@ -246,7 +246,7 @@ For example: Example ^^^^^^^ -.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_01.* +.. figure:: /_images/res/PRESENTATION_ExSyn/memory_01.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.ys @@ -257,7 +257,7 @@ Example :language: verilog :caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.v`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_02.* +.. figure:: /_images/res/PRESENTATION_ExSyn/memory_02.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.v @@ -315,7 +315,7 @@ Finally the :cmd:ref:`fsm_map` command can be used to convert the (optimized) The :cmd:ref:`techmap` command ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. figure:: ../../images/res/PRESENTATION_ExSyn/techmap_01.* +.. figure:: /_images/res/PRESENTATION_ExSyn/techmap_01.* :class: width-helper The :cmd:ref:`techmap` command replaces cells with implementations given as @@ -386,7 +386,7 @@ Example :language: yoscrypt :caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.ys`` -.. figure:: ../../images/res/PRESENTATION_ExSyn/abc_01.* +.. figure:: /_images/res/PRESENTATION_ExSyn/abc_01.* :class: width-helper Other special-purpose mapping commands diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst index 20add9bb5..6a3f8802e 100644 --- a/docs/source/introduction.rst +++ b/docs/source/introduction.rst @@ -37,7 +37,7 @@ domain of behavioural, rtl and logic synthesis. Yosys is designed to be extensible and therefore is a good basis for implementing custom synthesis tools for specialised tasks. -.. figure:: ../images/levels_of_abstraction.* +.. figure:: /_images/levels_of_abstraction.* :class: width-helper :name: fig:Levels_of_abstraction diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index 2c36778c8..2957a1c2f 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -181,7 +181,7 @@ Example: :language: yoscrypt :caption: ``docs/resources/PRESENTATION_ExAdv/select.ys`` -.. figure:: ../../../images/res/PRESENTATION_ExAdv/select.* +.. figure:: /_images/res/PRESENTATION_ExAdv/select.* :class: width-helper Interactive Design Investigation @@ -226,10 +226,10 @@ reorganizing a module in Yosys and checking the resulting circuit. xs %c %ci %D %c %ci:+[D] %D \ %ci*:-$dff xs %co %ci %d -.. figure:: ../../../images/res/PRESENTATION_ExOth/scrambler_p01.* +.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.* :class: width-helper -.. figure:: ../../../images/res/PRESENTATION_ExOth/scrambler_p02.* +.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p02.* :class: width-helper Analyzing the resulting circuit with :doc:`/cmd/eval`: diff --git a/docs/source/using_yosys/yosys_flows.rst b/docs/source/using_yosys/yosys_flows.rst index 633a8ec77..0bd824b20 100644 --- a/docs/source/using_yosys/yosys_flows.rst +++ b/docs/source/using_yosys/yosys_flows.rst @@ -41,12 +41,12 @@ The extract pass .. todo:: add/expand supporting text -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_00a.* :class: width-helper before `extract` -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_00b.* :class: width-helper after `extract` @@ -70,20 +70,20 @@ The extract pass :language: verilog :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v`` -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01a.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01a.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01b.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_02.v :language: verilog :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v`` -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02a.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02a.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02b.* :class: width-helper The wrap-extract-unwrap method @@ -169,10 +169,10 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v`` :lines: 1-6 :caption: ``test1`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v`` -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v @@ -180,15 +180,15 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v`` :lines: 8-13 :caption: ``test2`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v`` -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.* :class: width-helper Wrapping in ``test1``: -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.* :class: width-helper .. code:: yoscrypt @@ -200,12 +200,12 @@ Wrapping in ``test1``: -unsigned $__add_wrapper \ Y Y_WIDTH ;; -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.* :class: width-helper Wrapping in ``test2``: -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.* :class: width-helper .. code:: yoscrypt @@ -217,7 +217,7 @@ Wrapping in ``test2``: -unsigned $__add_wrapper \ Y Y_WIDTH ;; -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.* :class: width-helper Extract in ``test1``: @@ -235,10 +235,10 @@ Extract in ``test1``: -map %__macc_xilinx_xmap \ -swap $__add_wrapper A,B ;; -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1d.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1d.* :class: width-helper Extract in ``test2``: @@ -256,18 +256,18 @@ Extract in ``test2``: -map %__macc_xilinx_xmap \ -swap $__add_wrapper A,B ;; -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.* :class: width-helper Unwrap in ``test2``: -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.* :class: width-helper -.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2e.* +.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2e.* :class: width-helper .. code:: yoscrypt diff --git a/docs/source/yosys_internals/extensions.rst b/docs/source/yosys_internals/extensions.rst index 5ef4b5c90..68d023d64 100644 --- a/docs/source/yosys_internals/extensions.rst +++ b/docs/source/yosys_internals/extensions.rst @@ -60,7 +60,7 @@ provides. This document will focus on the much simpler version of RTLIL left after the commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``): -.. figure:: ../../images/simplified_rtlil.* +.. figure:: /_images/simplified_rtlil.* :class: width-helper :name: fig:Simplified_RTLIL diff --git a/docs/source/yosys_internals/flow/control_and_data.rst b/docs/source/yosys_internals/flow/control_and_data.rst index 69b7346b5..b2ec418ad 100644 --- a/docs/source/yosys_internals/flow/control_and_data.rst +++ b/docs/source/yosys_internals/flow/control_and_data.rst @@ -9,7 +9,7 @@ a predetermined order, each consuming the data generated by the last subsystem and generating the data for the next subsystem (see :numref:`Fig. %s `). -.. figure:: ../../../images/approach_flow.* +.. figure:: /_images/approach_flow.* :class: width-helper :name: fig:approach_flow diff --git a/docs/source/yosys_internals/flow/overview.rst b/docs/source/yosys_internals/flow/overview.rst index c1dddfcbb..1c2adc01c 100644 --- a/docs/source/yosys_internals/flow/overview.rst +++ b/docs/source/yosys_internals/flow/overview.rst @@ -40,7 +40,7 @@ possible it is key that (1) all passes operate on the same data structure (RTLIL) and (2) that this data structure is powerful enough to represent the design in different stages of the synthesis. -.. figure:: ../../../images/overview_flow.* +.. figure:: /_images/overview_flow.* :class: width-helper :name: fig:Overview_flow diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index 2c8af3ad3..72907c121 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation is then passed to the AST frontend that converts it to RTLIL data, as illustrated in :numref:`Fig. %s `. -.. figure:: ../../../images/verilog_flow.* +.. figure:: /_images/verilog_flow.* :class: width-helper :name: fig:Verilog_flow diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index 78fa47ba4..b6b437b90 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -23,7 +23,7 @@ pass is reading an auxiliary Verilog file such as a cell library, it might create an additional ``RTLIL::Design`` object and call the Verilog frontend with this other object to parse the cell library. -.. figure:: ../../../images/overview_rtlil.* +.. figure:: /_images/overview_rtlil.* :class: width-helper :name: fig:Overview_RTLIL diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst index d0aadbd4d..b89ca9cb9 100644 --- a/docs/source/yosys_internals/techmap.rst +++ b/docs/source/yosys_internals/techmap.rst @@ -134,7 +134,7 @@ Mapping OR3X1 :language: verilog :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v`` -.. figure:: ../../images/res/PRESENTATION_ExAdv/red_or3x1.* +.. figure:: /_images/res/PRESENTATION_ExAdv/red_or3x1.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_test.ys @@ -160,7 +160,7 @@ Conditional techmap Example: -.. figure:: ../../images/res/PRESENTATION_ExAdv/sym_mul.* +.. figure:: /_images/res/PRESENTATION_ExAdv/sym_mul.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_map.v @@ -199,7 +199,7 @@ Scripting in map modules Example: -.. figure:: ../../images/res/PRESENTATION_ExAdv/mymul.* +.. figure:: /_images/res/PRESENTATION_ExAdv/mymul.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_map.v @@ -229,7 +229,7 @@ Handling constant inputs Example: -.. figure:: ../../images/res/PRESENTATION_ExAdv/mulshift.* +.. figure:: /_images/res/PRESENTATION_ExAdv/mulshift.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_map.v @@ -260,7 +260,7 @@ Handling shorted inputs Example: -.. figure:: ../../images/res/PRESENTATION_ExAdv/addshift.* +.. figure:: /_images/res/PRESENTATION_ExAdv/addshift.* :class: width-helper .. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_map.v diff --git a/docs/static/custom.css b/docs/static/custom.css deleted file mode 100644 index 40a8c178f..000000000 --- a/docs/static/custom.css +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/docs/static/yosyshq.css b/docs/static/yosyshq.css deleted file mode 100644 index 91a15c129..000000000 --- a/docs/static/yosyshq.css +++ /dev/null @@ -1,78 +0,0 @@ -h1, h3, p.topic-title, .content li.toctree-l1 > a { - color: #d6368f !important; -} - -h2, p.admonition-title, dt, .content li.toctree-l2 > a { - color: #4b72b8; -} - -a { - color: #8857a3; -} - -a.current, a:hover, a.external { - color: #d6368f !important; -} - -a.external:hover { - text-decoration: underline; -} - -p { - text-align: justify; -} - -.vp-sidebar a { - color: #d6368f; -} - -.vp-sidebar li li a { - color: #4b72b8; -} - -.vp-sidebar li li li a { - color: #2c3e50; - font-weight: 400; -} - -.vp-sidebar h3 { - padding-left: 1.5rem !important; -} - -.vp-sidebar ul a { - padding-left: 1.5rem !important; -} - -.vp-sidebar ul ul a { - padding-left: 3rem !important; -} - -.vp-sidebar ul ul ul a { - padding-left: 4.5rem !important; -} - -.vp-sidebar .toctree-l1.current a { - border-left: 0.5rem solid #6ecbd7; -} - -.vp-sidebar .toctree-l1 a.current { - border-left: 0.5rem solid #8857a3; -} - -.injected .rst-current-version, .injected dt { - color: #6ecbd7 !important; -} - -.cmd.def .highlight-yoscrypt, .cmd.def .highlight pre { - padding: 0%; - margin: 0%; -} - -.cmd.def .highlight-none, .cmd.def .highlight pre { - padding-top: 0%; - margin-top: 0%; -} - -.width-helper { - max-width: 100%; -}