Moving images and static folders

Images now included relative to the `docs/source` folder instead of the rst file.
Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs).

docs/source/yosys_internals/extensions.rst

@@ -60,7 +60,7 @@ provides.
 This document will focus on the much simpler version of RTLIL left after the
 commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
 
-.. figure:: ../../images/simplified_rtlil.*
+.. figure:: /_images/simplified_rtlil.*
     :class: width-helper
     :name: fig:Simplified_RTLIL
 

docs/source/yosys_internals/flow/control_and_data.rst

@@ -9,7 +9,7 @@ a predetermined order, each consuming the data generated by the last subsystem
 and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
-.. figure:: ../../../images/approach_flow.*
+.. figure:: /_images/approach_flow.*
 	:class: width-helper
 	:name: fig:approach_flow
 

docs/source/yosys_internals/flow/overview.rst

@@ -40,7 +40,7 @@ possible it is key that (1) all passes operate on the same data structure
 (RTLIL) and (2) that this data structure is powerful enough to represent the
 design in different stages of the synthesis.
 
-.. figure:: ../../../images/overview_flow.*
+.. figure:: /_images/overview_flow.*
 	:class: width-helper
 	:name: fig:Overview_flow
 

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation
 is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
-.. figure:: ../../../images/verilog_flow.*
+.. figure:: /_images/verilog_flow.*
 	:class: width-helper
 	:name: fig:Verilog_flow
 

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -23,7 +23,7 @@ pass is reading an auxiliary Verilog file such as a cell library, it might
 create an additional ``RTLIL::Design`` object and call the Verilog frontend with
 this other object to parse the cell library.
 
-.. figure:: ../../../images/overview_rtlil.*
+.. figure:: /_images/overview_rtlil.*
 	:class: width-helper
 	:name: fig:Overview_RTLIL
 

docs/source/yosys_internals/techmap.rst

@@ -134,7 +134,7 @@ Mapping OR3X1
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/red_or3x1.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/red_or3x1.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_test.ys
@@ -160,7 +160,7 @@ Conditional techmap
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/sym_mul.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/sym_mul.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_map.v
@@ -199,7 +199,7 @@ Scripting in map modules
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/mymul.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/mymul.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_map.v
@@ -229,7 +229,7 @@ Handling constant inputs
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/mulshift.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/mulshift.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_map.v
@@ -260,7 +260,7 @@ Handling shorted inputs
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/addshift.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/addshift.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_map.v