Moving images and static folders

Images now included relative to the `docs/source` folder instead of the rst file.
Also makes sure to add the updated `yosyshq.css` (which as a sidenote has ended up as `custom.css` in most of the other docs).

docs/source/_images/011/example_out.tex

@@ -0,0 +1,18 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\node[inner sep=0pt] at (0,0)
+		{\includegraphics[width=\linewidth]{example_00.pdf}};
+	\node[inner sep=0pt] at (0,-3.8)
+		{\includegraphics[width=\linewidth]{example_01.pdf}};
+	\node[inner sep=0pt] at (0,-7)
+		{\includegraphics[width=\linewidth]{example_02.pdf}};
+\end{tikzpicture}
+\end{document}

docs/source/_images/011/select_prod.tex

@@ -0,0 +1,19 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\node[inner sep=0pt] at (0,0)
+		{\hfill \includegraphics[width=4cm,trim=0 1cm 0 1cm]{sumprod_02.pdf}};
+	\node[inner sep=0pt] at (0,-2.8)
+		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_03.pdf}};
+	\node[inner sep=0pt] at (0,-6.2)
+		{\includegraphics[width=\linewidth,trim=0 0cm 0 1cm]{sumprod_04.pdf}};
+	\node[inner sep=0pt] at (0,-9.2)
+		{\includegraphics[width=\linewidth,trim=0 1cm 0 1cm]{sumprod_05.pdf}};
+\end{tikzpicture}
+\end{document}

docs/source/_images/011/splitnets_libfile.tex

@@ -0,0 +1,15 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\node[inner sep=0pt] at (0,0)
+		{\includegraphics[height=\linewidth]{cmos_00.pdf}};
+	\node[inner sep=0pt] at (2,-8)
+		{\includegraphics[width=\linewidth]{cmos_01.pdf}};
+\end{tikzpicture}
+\end{document}

docs/source/_images/011/submod_dots.tex

@@ -0,0 +1,27 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\node[inner sep=0pt] at (0,0)
+		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_00.pdf}};
+	\node at (0, -2.5)
+		{\tt memdemo};
+	\node[inner sep=0pt] at (0,-5)
+		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_01.pdf}};
+	\node at (0, -7.5)
+		{\tt scramble};
+	\node[inner sep=0pt] at (0, -11)
+		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_02.pdf}};
+	\node at (0, -14.8)
+		{\tt outstage};
+	\node[inner sep=0pt] at (0,-16.6)
+		{\includegraphics[width=\linewidth,trim=0 1.3cm 0 0cm]{submod_03.pdf}};
+	\node at (0, -19)
+		{\tt selstage};
+\end{tikzpicture}
+\end{document}

docs/source/_images/Makefile

@@ -0,0 +1,61 @@
+all: resources dots tex svg tidy
+
+RES_LIST:= PRESENTATION_Intro/ PRESENTATION_ExSyn/ PRESENTATION_ExAdv/ PRESENTATION_ExOth/
+RES_DIRS:= $(addprefix ../resources/,$(RES_LIST))
+.PHONY: resources
+resources: $(RES_DIRS)
+FORCE:
+../resources/%: FORCE
+	@$(MAKE) -C $@
+	@mkdir -p res/$*
+	@cp --update -t res/$* $@*.dot
+
+TEX_SOURCE:= $(wildcard *.tex)
+DOT_LOC:= ../source/APPNOTE_011_Design_Investigation
+DOT_SOURCE:= $(wildcard $(DOT_LOC)/*.dot)
+
+RES_DOTS:= $(wildcard res/*/*.dot)
+RES_DIRS:= $(sort $(dir $(RES_DOTS)))
+RES_PDF:= $(RES_DOTS:%.dot=%.pdf)
+
+TEX_SOURCE+= 011/example_out.tex
+011/example_out.pdf: 011/example_00.pdf 011/example_01.pdf 011/example_02.pdf
+TEX_SOURCE+= 011/select_prod.tex
+011/select_prod.pdf: 011/sumprod_02.pdf 011/sumprod_03.pdf 011/sumprod_04.pdf 011/sumprod_05.pdf
+TEX_SOURCE+= 011/splitnets_libfile.tex
+011/splitnets_libfile.pdf: 011/cmos_00.pdf 011/cmos_01.pdf
+TEX_SOURCE+= 011/submod_dots.tex
+011/submod_dots.pdf: 011/submod_00.pdf 011/submod_01.pdf 011/submod_02.pdf 011/submod_03.pdf
+
+TEX_PDF:= $(patsubst %.tex,%.pdf,$(TEX_SOURCE))
+DOT_PDF:= $(addprefix 011/,$(notdir $(patsubst %.dot,%.pdf,$(DOT_SOURCE))))
+SVG_OUTPUT:= $(patsubst %.pdf,%.svg,$(TEX_PDF) $(DOT_PDF) $(RES_PDF))
+
+dots: $(DOT_PDF) $(RES_PDF)
+tex: $(TEX_PDF)
+svg: $(SVG_OUTPUT)
+
+011/%.pdf: $(DOT_LOC)/%.dot
+	faketime -f '2022-01-01 00:00:00 x0,001' dot -Tpdf -o $@ $<
+
+res/%.pdf: res/%.dot
+	faketime -f '2022-01-01 00:00:00 x0,001' dot -Tpdf -o $@ $<
+
+011/%.pdf: 011/%.tex
+	cd 011 && faketime -f '2022-01-01 00:00:00 x0,001' pdflatex $(<F) --interaction=nonstopmode
+
+%.pdf: %.tex
+	pdflatex $< --interaction=nonstopmode
+
+%.svg: %.pdf
+	pdf2svg $< $@
+
+.PHONY: clean tidy
+tidy:
+	rm -f *.log
+	rm -f *.aux
+	rm -f  011/*.log 011/*.aux
+clean: tidy
+	rm -f *.pdf
+	rm -f *.svg
+	rm -f 011/*.pdf 011/*.svg

docs/source/_images/approach_flow.tex

@@ -0,0 +1,38 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\usetikzlibrary{calc}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\path (-1.5,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+	\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Frontend} ++(1,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+	\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+	\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+	\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+	\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Backend} ++(1,3) coordinate (cursor);
+	\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
+
+	\path (-3,-0.5) coordinate (cursor);
+	\draw (cursor) -- node[below] {HDL} ++(3,0) coordinate (cursor);
+	\draw[|-|] (cursor) -- node[below] {Internal Format(s)} ++(8,0) coordinate (cursor);
+	\draw (cursor) -- node[below] {Netlist} ++(3,0);
+
+	\path (-3,3.5) coordinate (cursor);
+	\draw[-] (cursor) -- node[above] {High-Level} ++(3,0) coordinate (cursor);
+	\draw[-] (cursor) -- ++(8,0) coordinate (cursor);
+	\draw[->] (cursor) -- node[above] {Low-Level} ++(3,0);
+
+\end{tikzpicture}
+\end{document}

docs/source/_images/basics_abstractions.tex

@@ -0,0 +1,41 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{lvl} = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=15em]
+	\node[lvl] (sys) {System Level};
+	\node[lvl] (hl) [below of=sys] {High Level};
+	\node[lvl] (beh) [below of=hl] {Behavioral Level};
+	\node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
+	\node[lvl] (lg) [below of=rtl] {Logical Gate Level};
+	\node[lvl] (pg) [below of=lg] {Physical Gate Level};
+	\node[lvl] (sw) [below of=pg] {Switch Level};
+
+	\draw[dotted] (sys.east)  -- ++(1,0) coordinate (sysx);
+	\draw[dotted] (hl.east)  -- ++(1,0) coordinate (hlx);
+	\draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
+	\draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
+	\draw[dotted] (lg.east)  -- ++(1,0) coordinate (lgx);
+	\draw[dotted] (pg.east)  -- ++(1,0) coordinate (pgx);
+	\draw[dotted] (sw.east)  -- ++(1,0) coordinate (swx);
+
+	\draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
+	\draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
+	\draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
+	\draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
+	\draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
+	\draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
+
+	\draw[dotted] (behx) -- ++(5,0) coordinate (a);
+	\draw[dotted] (pgx) -- ++(5,0) coordinate (b);
+	\draw[|->|] (a) -- node[right] {Yosys} (b);
+\end{tikzpicture}
+\end{document}

docs/source/_images/basics_ast.tex

@@ -0,0 +1,30 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\usetikzlibrary{shapes.geometric}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{node} = [draw, fill=green!10, ellipse, minimum height=2em, minimum width=8em, node distance=10em]
+
+	\draw (+0,+0) node[node] (n1) {\tt ASSIGN};
+
+	\draw (-2,-2) node[node] (n11) {\tt ID: foo};
+	\draw (+2,-2) node[node] (n12) {\tt PLUS};
+
+	\draw (+0,-4) node[node] (n121) {\tt ID: bar};
+	\draw (+4,-4) node[node] (n122) {\tt CONST: 42};
+
+	\draw[-latex] (n1) -- (n11);
+	\draw[-latex] (n1) -- (n12);
+
+	\draw[-latex] (n12) -- (n121);
+	\draw[-latex] (n12) -- (n122);
+\end{tikzpicture}
+\end{document}

docs/source/_images/basics_flow.tex

@@ -0,0 +1,44 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{manual} = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=8em, node distance=10em]
+	\tikzstyle{auto} = [draw, fill=orange!10, rectangle, minimum height=2em, minimum width=8em, node distance=10em]
+
+	\node[manual] (sys) {\begin{minipage}{8em}
+		\center
+		System Level \\
+		Model
+	\end{minipage}};
+	\node[manual] (beh) [right of=sys] {\begin{minipage}{8em}
+		\center
+		Behavioral \\
+		Model
+	\end{minipage}};
+	\node[auto] (rtl) [right of=beh] {\begin{minipage}{8em}
+		\center
+		RTL \\
+		Model
+	\end{minipage}};
+	\node[auto] (gates) [right of=rtl] {\begin{minipage}{8em}
+		\center
+		Gate-Level \\
+		Model
+	\end{minipage}};
+
+	\draw[-latex] (beh) edge[double, bend left] node[above] {synthesis} (rtl);
+	\draw[-latex] (rtl) edge[double, bend left] node[above] {synthesis} (gates);
+
+	\draw[latex-latex] (sys) edge[bend right] node[below] {verify} (beh);
+	\draw[latex-latex] (beh) edge[bend right] node[below] {verify} (rtl);
+	\draw[latex-latex] (rtl) edge[bend right] node[below] {verify} (gates);
+\end{tikzpicture}
+\end{document}

docs/source/_images/basics_parsetree.tex

@@ -0,0 +1,44 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\usetikzlibrary{shapes.geometric}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{node} = [draw, fill=green!10, ellipse, minimum height=2em, minimum width=8em, node distance=10em]
+
+	\draw (+0,+1) node[node] (n1) {\tt assign\_stmt};
+
+	\draw (-6,-1) node[node] (n11) {\tt TOK\_ASSIGN};
+	\draw (-3,-2) node[node] (n12) {\tt TOK\_IDENTIFIER};
+	\draw (+0,-1) node[node] (n13) {\tt TOK\_EQ};
+	\draw (+3,-2) node[node] (n14) {\tt expr};
+	\draw (+6,-1) node[node] (n15) {\tt TOK\_SEMICOLON};
+
+	\draw (-1,-4) node[node] (n141) {\tt expr};
+	\draw (+3,-4) node[node] (n142) {\tt TOK\_PLUS};
+	\draw (+7,-4) node[node] (n143) {\tt expr};
+
+	\draw (-1,-5.5) node[node] (n1411) {\tt TOK\_IDENTIFIER};
+	\draw (+7,-5.5) node[node] (n1431) {\tt TOK\_NUMBER};
+
+	\draw[-latex] (n1) -- (n11);
+	\draw[-latex] (n1) -- (n12);
+	\draw[-latex] (n1) -- (n13);
+	\draw[-latex] (n1) -- (n14);
+	\draw[-latex] (n1) -- (n15);
+
+	\draw[-latex] (n14) -- (n141);
+	\draw[-latex] (n14) -- (n142);
+	\draw[-latex] (n14) -- (n143);
+
+	\draw[-latex] (n141) -- (n1411);
+	\draw[-latex] (n143) -- (n1431);
+\end{tikzpicture}
+\end{document}

docs/source/_images/levels_of_abstraction.tex

@@ -0,0 +1,42 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+\definecolor{MyBlue}{RGB}{85,130,180}
+
+\begin{document}
+\begin{tikzpicture}[scale=1.2, every node/.style={transform shape}]
+    \tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
+    \node[lvl] (sys) {System Level};
+    \node[lvl] (hl) [below of=sys] {High Level};
+    \node[lvl] (beh) [below of=hl] {Behavioral Level};
+    \node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
+    \node[lvl] (lg) [below of=rtl] {Logical Gate Level};
+    \node[lvl] (pg) [below of=lg] {Physical Gate Level};
+    \node[lvl] (sw) [below of=pg] {Switch Level};
+
+    \draw[dotted] (sys.east)  -- ++(1,0) coordinate (sysx);
+    \draw[dotted] (hl.east)  -- ++(1,0) coordinate (hlx);
+    \draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
+    \draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
+    \draw[dotted] (lg.east)  -- ++(1,0) coordinate (lgx);
+    \draw[dotted] (pg.east)  -- ++(1,0) coordinate (pgx);
+    \draw[dotted] (sw.east)  -- ++(1,0) coordinate (swx);
+
+    \draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
+    \draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
+    \draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
+    \draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
+    \draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
+    \draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
+
+    \draw[dotted] (behx) -- ++(4,0) coordinate (a);
+    \draw[dotted] (pgx) -- ++(4,0) coordinate (b);
+    \draw[|->|] (a) -- node[right] {Yosys} (b);
+\end{tikzpicture}
+\end{document}

docs/source/_images/overview_flow.tex

@@ -0,0 +1,37 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\usetikzlibrary{shapes.geometric}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
+	\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
+	\node[process] (vlog) {Verilog Frontend};
+	\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
+	\node[process] (ilang) [right of=vhdl] {RTLIL Frontend};
+	\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
+	\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
+	\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
+	\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
+	\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
+	\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
+	\node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
+
+	\draw[-latex] (vlog) -- (ast);
+	\draw[-latex] (vhdl) -- (ast);
+	\draw[-latex] (ast) -- (astfe);
+	\draw[-latex] (astfe) -- (rtlil);
+	\draw[-latex] (ilang) -- (rtlil);
+	\draw[latex-latex] (rtlil) -- (pass);
+	\draw[-latex] (rtlil) -- (vlbe);
+	\draw[-latex] (rtlil) -- (ilangbe);
+	\draw[-latex] (rtlil) -- (otherbe);
+\end{tikzpicture}
+\end{document}

docs/source/_images/overview_rtlil.tex

@@ -0,0 +1,27 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
+	\node[entity] (design) {RTLIL::Design};
+	\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
+
+	\node[entity] (process) [fill=green!10, right of=module, node distance=10em] {RTLIL::Process} (process.west) edge [-latex] (module);
+	\node[entity] (memory) [fill=red!10, below of=process] {RTLIL::Memory} edge [-latex] (module);
+	\node[entity] (wire) [fill=blue!10, above of=process] {RTLIL::Wire} (wire.west) edge [-latex] (module);
+	\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
+
+	\node[entity] (case) [fill=green!10, right of=process, node distance=10em] {RTLIL::CaseRule} edge [latex-latex] (process);
+	\node[entity] (sync) [fill=green!10, above of=case] {RTLIL::SyncRule} edge [-latex] (process);
+	\node[entity] (switch) [fill=green!10, below of=case] {RTLIL::SwitchRule} edge [-latex] (case);
+	\draw[latex-] (switch.east) -- ++(1em,0) |- (case.east);
+\end{tikzpicture}
+\end{document}

docs/source/_images/simplified_rtlil.tex

@@ -0,0 +1,20 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}[every node/.style={transform shape}]
+	\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
+	\node[entity] (design) {RTLIL::Design};
+	\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
+
+	\node[entity] (wire) [fill=blue!10, right of=module, node distance=10em] {RTLIL::Wire} (wire.west) edge [-latex] (module);
+	\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
+\end{tikzpicture}
+\end{document}

docs/source/_images/verilog_flow.tex

@@ -0,0 +1,67 @@
+\documentclass[12pt,tikz]{standalone}
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
+\usepackage[utf8]{inputenc}
+\usepackage{amsmath}
+\usepackage{pgfplots}
+\usepackage{tikz}
+\usetikzlibrary{shapes.geometric}
+\pagestyle{empty}
+
+\begin{document}
+\begin{tikzpicture}
+	\tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=5em, font={\ttfamily}]
+	\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
+
+	\node[data]    (n1)               {Verilog Source};
+	\node[process] (n2) [below of=n1] {Verilog Frontend};
+	\node[data]    (n3) [below of=n2] {AST};
+	\node[process] (n4) [below of=n3] {AST Frontend};
+	\node[data]    (n5) [below of=n4] {RTLIL};
+
+	\draw[-latex] (n1) -- (n2);
+	\draw[-latex] (n2) -- (n3);
+	\draw[-latex] (n3) -- (n4);
+	\draw[-latex] (n4) -- (n5);
+
+	\tikzstyle{details} = [draw, fill=yellow!5, rectangle, node distance=6cm, font={\ttfamily}]
+
+	\node[details] (d1) [right of=n2] {\begin{minipage}{5cm}
+		\hfil
+		\begin{tikzpicture}
+			\tikzstyle{subproc} = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=10em, node distance=3em, font={\ttfamily}]
+			\node (s0) {};
+			\node[subproc] (s1) [below of=s0] {Preprocessor};
+			\node[subproc] (s2) [below of=s1] {Lexer};
+			\node[subproc] (s3) [below of=s2] {Parser};
+			\node[node distance=3em] (s4) [below of=s3] {};
+			\draw[-latex] (s0) -- (s1);
+			\draw[-latex] (s1) -- (s2);
+			\draw[-latex] (s2) -- (s3);
+			\draw[-latex] (s3) -- (s4);
+		\end{tikzpicture}
+	\end{minipage}};
+
+	\draw[dashed] (n2.north east) -- (d1.north west);
+	\draw[dashed] (n2.south east) -- (d1.south west);
+
+	\node[details] (d2) [right of=n4] {\begin{minipage}{5cm}
+		\hfil
+		\begin{tikzpicture}
+			\tikzstyle{subproc} = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=10em, node distance=3em, font={\ttfamily}]
+			\node (s0) {};
+			\node[subproc] (s1) [below of=s0] {Simplifier};
+			\node[subproc] (s2) [below of=s1] {RTLIL Generator};
+			\node[node distance=3em] (s3) [below of=s2] {};
+			\draw[-latex] (s0) -- (s1);
+			\draw[-latex] (s1) -- (s2);
+			\draw[-latex] (s2) -- (s3);
+		\end{tikzpicture}
+	\end{minipage}};
+
+	\draw[dashed] (n4.north east) -- (d2.north west);
+	\draw[dashed] (n4.south east) -- (d2.south west);
+
+\end{tikzpicture}
+\end{document}

docs/source/_static/custom.css

@@ -0,0 +1,15 @@
+/* Reduce whitespace in cmd def pages */
+.cmd.def .highlight-yoscrypt, .cmd.def .highlight pre {
+    padding: 0%;
+    margin: 0%;
+}
+
+.cmd.def .highlight-none, .cmd.def .highlight pre {
+    padding-top: 0%;
+    margin-top: 0%;
+}
+
+/* Make images full width */
+.width-helper {
+    max-width: 100%;
+}  

docs/source/_static/yosyshq.css

@@ -0,0 +1,26 @@
+/* Don't hide the right sidebar as we're placing our fixed links there */
+aside.no-toc {
+    display: block !important;
+}
+
+/* Colorful headings */
+h1 {
+    color: var(--color-brand-primary);
+  }
+  
+h2, h3, h4, h5, h6 {
+    color: var(--color-brand-content);
+}
+
+/* Use a different color for external links */
+a.external {
+    color: var(--color-brand-primary) !important;
+}
+
+.wy-table-responsive table td {
+    white-space: normal;
+}
+  
+th {
+    text-align: left;
+}

docs/source/appendix/APPNOTE_011_Design_Investigation.rst

@@ -60,7 +60,7 @@ Introduction to the show command
                y <= c ? a + b : 2'd0;
    endmodule
 
-.. figure:: ../../images/011/example_out.*
+.. figure:: /_images/011/example_out.*
    :class: width-helper
    :name: example_out
    
@@ -134,7 +134,7 @@ leads us to the 3rd diagram in :numref:`example_out`. Here we see that the
 :cmd:ref:`proc`, but also determined correctly that it can remove the first
 ``$mux`` cell without changing the behavior of the circuit.
 
-.. figure:: ../../images/011/splice.*
+.. figure:: /_images/011/splice.*
    :class: width-helper
    :name: splice_dia
 
@@ -144,7 +144,7 @@ leads us to the 3rd diagram in :numref:`example_out`. Here we see that the
    :caption: ``splice.v``
    :name: splice_src
 
-.. figure:: ../../images/011/splitnets_libfile.*
+.. figure:: /_images/011/splitnets_libfile.*
    :class: width-helper
    :name: splitnets_libfile
 
@@ -329,7 +329,7 @@ run from module-context and not design-context.
 Working with selections
 -----------------------
 
-.. figure:: ../../images/011/example_03.*
+.. figure:: /_images/011/example_03.*
    :class: width-helper
    :name: seladd
 
@@ -386,7 +386,7 @@ Operations on selections
    :name: sumprod
    :language: verilog
 
-.. figure:: ../../images/011/sumprod_00.*
+.. figure:: /_images/011/sumprod_00.*
    :class: width-helper
    :name: sumprod_00
 
@@ -434,7 +434,7 @@ be achieved using the ``%x`` action, that broadens the selection, i.e. for each
 selected wire it selects all cells connected to the wire and vice versa. So
 ``show a:sumstuff %x`` yields the diagram shown in :numref:`sumprod_01`.
 
-.. figure:: ../../images/011/sumprod_01.*
+.. figure:: /_images/011/sumprod_01.*
    :class: width-helper
    :name: sumprod_01
 
@@ -471,7 +471,7 @@ performing the ``%ci`` action three times.
 The action ``%ci*`` performs the ``%ci`` action over and over again until it
 has no effect anymore.
 
-.. figure:: ../../images/011/select_prod.*
+.. figure:: /_images/011/select_prod.*
    :class: width-helper
    :name: select_prod
    
@@ -493,7 +493,7 @@ see the diagram shown in :numref:`memdemo_00`.
    :name: memdemo_src
    :language: verilog
 
-.. figure:: ../../images/011/memdemo_00.*
+.. figure:: /_images/011/memdemo_00.*
    :class: width-helper
    :name: memdemo_00
    
@@ -538,7 +538,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
 
    show y %ci2:-[CLK]
 
-.. figure:: ../../images/011/memdemo_01.*
+.. figure:: /_images/011/memdemo_01.*
    :class: width-helper
    :name: memdemo_01
    
@@ -616,7 +616,7 @@ the circuit from :numref:`memdemo_src` and :numref:`memdemo_00` into its
 components. The ``-name`` option is used to specify the name of the new module
 and also the name of the new cell in the current module.
 
-.. figure:: ../../images/011/submod_dots.*
+.. figure:: /_images/011/submod_dots.*
    :class: width-helper
    :name: submod_dots
 

docs/source/appendix/primer.rst

@@ -23,7 +23,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
 :numref:`Figure %s <fig:Basics_abstractions>` lists the different levels of
 abstraction and how they relate to different kinds of synthesis.
 
-.. figure:: ../../images/basics_abstractions.*
+.. figure:: /_images/basics_abstractions.*
 	:class: width-helper
 	:name: fig:Basics_abstractions
 
@@ -498,7 +498,7 @@ Then the synthesizable description is transformed to lower-level representations
 using a series of tools and the results are again verified using simulation.
 This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
 
-.. figure:: ../../images/basics_flow.*
+.. figure:: /_images/basics_flow.*
 	:class: width-helper
 	:name: fig:Basics_flow
 
@@ -597,7 +597,7 @@ Let's consider the following BNF (in Bison syntax):
    assign_stmt: TOK_ASSIGN TOK_IDENTIFIER TOK_EQ expr TOK_SEMICOLON;
    expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
 
-.. figure:: ../../images/basics_parsetree.*
+.. figure:: /_images/basics_parsetree.*
 	:class: width-helper
 	:name: fig:Basics_parsetree
 
@@ -626,7 +626,7 @@ Usually the AST is then converted into yet another representation that is more
 suitable for further processing. In compilers this is often an assembler-like
 three-address-code intermediate representation. :cite:p:`Dragonbook`
 
-.. figure:: ../../images/basics_ast.*
+.. figure:: /_images/basics_ast.*
 	:class: width-helper
 	:name: fig:Basics_ast
 

docs/source/conf.py

@@ -9,8 +9,8 @@ copyright ='2022 YosysHQ GmbH'
 # select HTML theme
 html_theme = 'furo'
 templates_path = ["_templates"]
-html_logo = '../static/logo.png'
-html_favicon = '../static/favico.png'
+html_logo = '_static/logo.png'
+html_favicon = '_static/favico.png'
 html_css_files = ['yosyshq.css', 'custom.css']
 
 html_theme_options = {
@@ -34,7 +34,7 @@ html_theme_options = {
 }
 
 # These folders are copied to the documentation's HTML output
-html_static_path = ['../static', "../images"]
+html_static_path = ['_static', "_images"]
 
 # code blocks style 
 pygments_style = 'colorful'

docs/source/getting_started/examples.rst

@@ -106,7 +106,7 @@ Step 1
 
 Result:
 
-.. figure:: ../../images/res/PRESENTATION_Intro/counter_00.*
+.. figure:: /_images/res/PRESENTATION_Intro/counter_00.*
     :class: width-helper
 
 Step 2
@@ -118,7 +118,7 @@ Step 2
 
 Result:
 
-.. figure:: ../../images/res/PRESENTATION_Intro/counter_01.*
+.. figure:: /_images/res/PRESENTATION_Intro/counter_01.*
     :class: width-helper
 
 Step 3
@@ -130,7 +130,7 @@ Step 3
 
 Result:
 
-.. figure:: ../../images/res/PRESENTATION_Intro/counter_02.*
+.. figure:: /_images/res/PRESENTATION_Intro/counter_02.*
     :class: width-helper
 
 Step 4
@@ -142,5 +142,5 @@ Step 4
 
 Result:
 
-.. figure:: ../../images/res/PRESENTATION_Intro/counter_03.*
+.. figure:: /_images/res/PRESENTATION_Intro/counter_03.*
     :class: width-helper

docs/source/getting_started/typical_phases.rst

@@ -94,10 +94,10 @@ Example
    :language: yoscrypt
    :caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.ys``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_01.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/proc_01.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_02.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/proc_02.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.v
@@ -108,7 +108,7 @@ Example
    :language: yoscrypt
    :caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.ys``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/proc_03.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/proc_03.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.ys
@@ -150,7 +150,7 @@ The command :cmd:ref:`clean` can be used as alias for :cmd:ref:`opt_clean`. And
 Example
 ^^^^^^^
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_01.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/opt_01.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.ys
@@ -161,7 +161,7 @@ Example
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_02.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/opt_02.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.ys
@@ -172,7 +172,7 @@ Example
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_03.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/opt_03.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.ys
@@ -183,7 +183,7 @@ Example
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/opt_04.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/opt_04.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.v
@@ -246,7 +246,7 @@ For example:
 Example
 ^^^^^^^
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_01.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/memory_01.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.ys
@@ -257,7 +257,7 @@ Example
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/memory_02.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/memory_02.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.v
@@ -315,7 +315,7 @@ Finally the :cmd:ref:`fsm_map` command can be used to convert the (optimized)
 The :cmd:ref:`techmap` command
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/techmap_01.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/techmap_01.*
     :class: width-helper
 
 The :cmd:ref:`techmap` command replaces cells with implementations given as
@@ -386,7 +386,7 @@ Example
    :language: yoscrypt
    :caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.ys``
 
-.. figure:: ../../images/res/PRESENTATION_ExSyn/abc_01.*
+.. figure:: /_images/res/PRESENTATION_ExSyn/abc_01.*
     :class: width-helper
 
 Other special-purpose mapping commands

docs/source/introduction.rst

@@ -37,7 +37,7 @@ domain of behavioural, rtl and logic synthesis. Yosys is designed to be
 extensible and therefore is a good basis for implementing custom synthesis tools
 for specialised tasks.
 
-.. figure:: ../images/levels_of_abstraction.*
+.. figure:: /_images/levels_of_abstraction.*
     :class: width-helper
     :name: fig:Levels_of_abstraction
 

docs/source/using_yosys/more_scripting/selections.rst

@@ -181,7 +181,7 @@ Example:
    :language: yoscrypt
    :caption: ``docs/resources/PRESENTATION_ExAdv/select.ys``
 
-.. figure:: ../../../images/res/PRESENTATION_ExAdv/select.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/select.*
     :class: width-helper
 
 Interactive Design Investigation
@@ -226,10 +226,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
             xs %c %ci %D %c %ci:+[D] %D \
             %ci*:-$dff xs %co %ci %d
 
-.. figure:: ../../../images/res/PRESENTATION_ExOth/scrambler_p01.*
+.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
     :class: width-helper
 
-.. figure:: ../../../images/res/PRESENTATION_ExOth/scrambler_p02.*
+.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p02.*
     :class: width-helper
 
 Analyzing the resulting circuit with :doc:`/cmd/eval`:

docs/source/using_yosys/yosys_flows.rst

@@ -41,12 +41,12 @@ The extract pass
 
 .. todo:: add/expand supporting text
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
     :class: width-helper
     
     before `extract`
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_00b.*
     :class: width-helper
     
     after `extract`
@@ -70,20 +70,20 @@ The extract pass
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01a.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01a.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01b.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_02.v
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02a.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02a.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02b.*
     :class: width-helper
 
 The wrap-extract-unwrap method
@@ -169,10 +169,10 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
    :lines: 1-6
    :caption: ``test1`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -180,15 +180,15 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
    :lines: 8-13
    :caption: ``test2`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
     :class: width-helper
 
 Wrapping in ``test1``:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
     :class: width-helper
 
 .. code:: yoscrypt
@@ -200,12 +200,12 @@ Wrapping in ``test1``:
                 -unsigned $__add_wrapper \
                                 Y Y_WIDTH ;;
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
     :class: width-helper
 
 Wrapping in ``test2``:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
     :class: width-helper
 
 .. code:: yoscrypt
@@ -217,7 +217,7 @@ Wrapping in ``test2``:
                  -unsigned $__add_wrapper \
                                 Y Y_WIDTH ;;
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
     :class: width-helper
 
 Extract in ``test1``:
@@ -235,10 +235,10 @@ Extract in ``test1``:
             -map %__macc_xilinx_xmap       \
             -swap $__add_wrapper A,B ;;
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1d.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1d.*
     :class: width-helper
 
 Extract in ``test2``:
@@ -256,18 +256,18 @@ Extract in ``test2``:
             -map %__macc_xilinx_xmap       \
             -swap $__add_wrapper A,B ;;
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
     :class: width-helper
 
 Unwrap in ``test2``:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
     :class: width-helper
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2e.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2e.*
     :class: width-helper
 
 .. code:: yoscrypt

docs/source/yosys_internals/extensions.rst

@@ -60,7 +60,7 @@ provides.
 This document will focus on the much simpler version of RTLIL left after the
 commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
 
-.. figure:: ../../images/simplified_rtlil.*
+.. figure:: /_images/simplified_rtlil.*
     :class: width-helper
     :name: fig:Simplified_RTLIL
 

docs/source/yosys_internals/flow/control_and_data.rst

@@ -9,7 +9,7 @@ a predetermined order, each consuming the data generated by the last subsystem
 and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
-.. figure:: ../../../images/approach_flow.*
+.. figure:: /_images/approach_flow.*
 	:class: width-helper
 	:name: fig:approach_flow
 

docs/source/yosys_internals/flow/overview.rst

@@ -40,7 +40,7 @@ possible it is key that (1) all passes operate on the same data structure
 (RTLIL) and (2) that this data structure is powerful enough to represent the
 design in different stages of the synthesis.
 
-.. figure:: ../../../images/overview_flow.*
+.. figure:: /_images/overview_flow.*
 	:class: width-helper
 	:name: fig:Overview_flow
 

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation
 is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
-.. figure:: ../../../images/verilog_flow.*
+.. figure:: /_images/verilog_flow.*
 	:class: width-helper
 	:name: fig:Verilog_flow
 

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -23,7 +23,7 @@ pass is reading an auxiliary Verilog file such as a cell library, it might
 create an additional ``RTLIL::Design`` object and call the Verilog frontend with
 this other object to parse the cell library.
 
-.. figure:: ../../../images/overview_rtlil.*
+.. figure:: /_images/overview_rtlil.*
 	:class: width-helper
 	:name: fig:Overview_RTLIL
 

docs/source/yosys_internals/techmap.rst

@@ -134,7 +134,7 @@ Mapping OR3X1
    :language: verilog
    :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v``
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/red_or3x1.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/red_or3x1.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_test.ys
@@ -160,7 +160,7 @@ Conditional techmap
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/sym_mul.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/sym_mul.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_map.v
@@ -199,7 +199,7 @@ Scripting in map modules
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/mymul.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/mymul.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_map.v
@@ -229,7 +229,7 @@ Handling constant inputs
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/mulshift.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/mulshift.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_map.v
@@ -260,7 +260,7 @@ Handling shorted inputs
 
 Example:
 
-.. figure:: ../../images/res/PRESENTATION_ExAdv/addshift.*
+.. figure:: /_images/res/PRESENTATION_ExAdv/addshift.*
     :class: width-helper
 
 .. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_map.v