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Towards DRAM support in Xilinx flow

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Clifford Wolf 2015-04-09 08:17:14 +02:00
parent 21a1cc1b60
commit b00cad81d7
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techlibs/xilinx/drams_bb.v Normal file
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module RAM32X1D (
output DPO, SPO,
input A0, A1, A2, A3, A4, D,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
input WCLK, WE
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule