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12 lines
203 B
Verilog
12 lines
203 B
Verilog
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module RAM32X1D (
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output DPO, SPO,
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input A0, A1, A2, A3, A4, D,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
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input WCLK, WE
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);
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parameter INIT = 32'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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endmodule
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