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Fixup README.

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nella 2026-07-24 10:45:03 +02:00 • committed by nella
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docs/source/using_yosys/verilog.rst
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@ -175,7 +175,7 @@ Verilog Attributes and non-standard features
``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt
from the ``proc -latches <info|warn|error>`` reporting policy, and the from the ``proc -latches <info|warn|error>`` reporting policy, and the
generated latch cells carry the ``always_latch`` attribute, which also generated latch cells carry the ``always_latch`` attribute, which also
exempts them from `check` ``-nolatches``/``-latchonly``. exempts them from `check` ``-nolatches``.
- The cell attribute ``wildcard_port_conns`` represents wildcard port - The cell attribute ``wildcard_port_conns`` represents wildcard port
connections (SystemVerilog ``.*``). These are resolved to concrete connections connections (SystemVerilog ``.*``). These are resolved to concrete connections