From affceca7df459f249d9e5b3534a321fd2beba105 Mon Sep 17 00:00:00 2001 From: nella Date: Fri, 24 Jul 2026 10:45:03 +0200 Subject: [PATCH] Fixup README. --- docs/source/using_yosys/verilog.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index 20f697cec..c503bd182 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -175,7 +175,7 @@ Verilog Attributes and non-standard features ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt from the ``proc -latches `` reporting policy, and the generated latch cells carry the ``always_latch`` attribute, which also - exempts them from `check` ``-nolatches``/``-latchonly``. + exempts them from `check` ``-nolatches``. - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete connections