mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-31 14:27:56 +00:00
Code Activity

verific: add option to disable splitting of complex ports

Browse source
This commit is contained in:
Dhaval Chaudhari 2026-01-04 12:06:23 +05:30
parent 8101c87fab
commit af810b3449
1 changed files with 8 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

10
frontends/verific/verific.cc
View file

@ -109,6 +109,7 @@ int verific_verbose;
bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
bool verific_no_split_complex_ports = false; // disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg);
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
VerificExtNets worker;
for (auto nl : nl_todo)
@ -3693,6 +3695,10 @@ struct VerificPass : public Pass {
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::UNDEFINED;