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https://github.com/YosysHQ/yosys
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Add opt_dff pass.
This commit is contained in:
Marcelina Kościelnicka
parent
8fd43515c5
commit
af6623ebb8
12 changed files with 1790 additions and 3 deletions
304
tests/opt/opt_dff_sr.ys
Normal file
304
tests/opt/opt_dff_sr.ys
Normal file
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@ -0,0 +1,304 @@
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### Always-active SET/CLR removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input CLR;
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input SET;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 1 t:$dffsr
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select -assert-count 1 t:$dffsr r:WIDTH=2 %i
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select -assert-count 1 t:$dffsre
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select -assert-count 1 t:$dffsre r:WIDTH=2 %i
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select -assert-count 1 t:$dlatchsr
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select -assert-count 1 t:$dlatchsr r:WIDTH=2 %i
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select -assert-none t:$sr
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design -load orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$dffsr
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select -assert-count 1 t:$dffsr r:WIDTH=4 %i
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select -assert-count 1 t:$dffsre
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select -assert-count 1 t:$dffsre r:WIDTH=4 %i
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select -assert-count 1 t:$dlatchsr
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select -assert-count 1 t:$dlatchsr r:WIDTH=4 %i
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select -assert-count 1 t:$sr
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select -assert-count 1 t:$sr r:WIDTH=4 %i
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 1 t:$_DFF_PP0_
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select -assert-count 1 t:$_DFF_PP1_
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select -assert-count 1 t:$_DFFE_PN0P_
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select -assert-count 1 t:$_DFFE_PN1P_
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select -assert-count 1 t:$_DLATCH_PP0_
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select -assert-count 1 t:$_DLATCH_PN1_
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select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_NOT_ %% %n t:* %i
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$_DFF_PP0_
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select -assert-count 1 t:$_DFF_PP1_
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select -assert-count 2 t:$_DFFSR_PPP_
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select -assert-count 1 t:$_DFFE_PN0P_
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select -assert-count 1 t:$_DFFE_PN1P_
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select -assert-count 2 t:$_DFFSRE_PNNP_
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select -assert-count 1 t:$_DLATCH_PP0_
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select -assert-count 1 t:$_DLATCH_PN1_
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select -assert-count 2 t:$_DLATCHSR_PNP_
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select -assert-count 1 t:$_DLATCH_P_
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select -assert-count 1 t:$_DLATCH_N_
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select -assert-count 2 t:$_SR_PN_
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select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFSR_PPP_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DFFSRE_PNNP_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_DLATCHSR_PNP_ t:$_NOT_ t:$_DLATCH_N_ t:$_DLATCH_P_ t:$_SR_PN_ %% %n t:* %i
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design -reset
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### Never-active CLR removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input CLR;
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input SET;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({6{SET}}), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({6{SET}}), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({6{SET}}), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({6{SET}}), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 0 t:$dffsr
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select -assert-count 0 t:$dffsre
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select -assert-count 0 t:$dlatchsr
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select -assert-count 0 t:$sr
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$adlatch
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select -assert-count 1 t:$dlatch
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design -reset
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### Never-active CLR removal (not applicable).
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input CLR;
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input SET;
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input ALT;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({{5{SET}}, ALT}), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({{5{SET}}, ALT}), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$dffsr
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select -assert-count 1 t:$dffsre
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select -assert-count 1 t:$dlatchsr
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select -assert-count 1 t:$sr
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select -assert-count 0 t:$adff
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select -assert-count 0 t:$adffe
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select -assert-count 0 t:$adlatch
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select -assert-count 0 t:$dlatch
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 0 t:$_DFFSR_*
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select -assert-count 0 t:$_DFFSRE_*
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select -assert-count 0 t:$_DLATCHSR_*
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select -assert-count 0 t:$_SR_*
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select -assert-count 6 t:$_DFF_PP1_
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select -assert-count 6 t:$_DFFE_PN1P_
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select -assert-count 6 t:$_DLATCH_PN1_
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select -assert-count 6 t:$_DLATCH_P_
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design -reset
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### Never-active SET removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input CLR;
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input SET;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({6{CLR}}), .SET(6'h00), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({6{CLR}}), .SET(6'h00), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 0 t:$dffsr
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select -assert-count 0 t:$dffsre
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select -assert-count 0 t:$dlatchsr
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select -assert-count 0 t:$sr
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$adlatch
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select -assert-count 1 t:$dlatch
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design -reset
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### Never-active CLR removal (not applicable).
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input CLR;
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input SET;
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input ALT;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({{5{CLR}}, ALT}), .SET(6'h00), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({{5{CLR}}, ALT}), .SET(6'h00), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$dffsr
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select -assert-count 1 t:$dffsre
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select -assert-count 1 t:$dlatchsr
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select -assert-count 1 t:$sr
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select -assert-count 0 t:$adff
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select -assert-count 0 t:$adffe
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select -assert-count 0 t:$adlatch
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select -assert-count 0 t:$dlatch
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 0 t:$_DFFSR_*
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select -assert-count 0 t:$_DFFSRE_*
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select -assert-count 0 t:$_DLATCHSR_*
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select -assert-count 0 t:$_SR_*
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select -assert-count 6 t:$_DFF_PP0_
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select -assert-count 6 t:$_DFFE_PN0P_
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select -assert-count 6 t:$_DLATCH_PP0_
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select -assert-count 6 t:$_DLATCH_N_
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design -reset
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### SET/CLR merge into ARST.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [5:0] D;
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output [23:0] Q;
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input ARST;
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input EN;
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$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({ARST, 5'h00}), .SET({1'b0, {5{ARST}}}), .D(D), .Q(Q[5:0]));
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$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({ARST, 5'h1f}), .SET({1'b1, {5{ARST}}}), .Q(Q[11:6]));
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$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({ARST, 5'h00}), .SET({1'b1, {5{ARST}}}), .Q(Q[17:12]));
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$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({ARST, 5'h1f}), .SET({1'b0, {5{ARST}}}), .Q(Q[23:18]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 0 t:$dffsr
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select -assert-count 0 t:$dffsre
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select -assert-count 1 t:$dlatchsr
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select -assert-count 1 t:$sr
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$adff r:ARST_VALUE=6'h1f %i
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$adffe r:ARST_VALUE=6'h1f %i
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select -assert-count 0 t:$adlatch
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select -assert-count 0 t:$dlatch
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