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https://github.com/YosysHQ/yosys
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verilog_backend: Add handling for all FF types.
This commit is contained in:
Marcelina Kościelnicka
parent
2f50c5af48
commit
8fd43515c5
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@ -25,6 +25,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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#include <string>
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#include <sstream>
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#include <set>
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@ -36,7 +37,7 @@ PRIVATE_NAMESPACE_BEGIN
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog;
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int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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std::set<RTLIL::IdString> reg_wires;
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std::string auto_prefix, extmem_prefix;
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RTLIL::Module *active_module;
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@ -451,7 +452,7 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b
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std::string cellname(RTLIL::Cell *cell)
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{
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if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort(ID::Q))
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if (!norename && cell->name[0] == '$' && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_)))
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{
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RTLIL::SigSpec sig = cell->getPort(ID::Q);
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if (GetSize(sig) != 1 || sig.is_fully_const())
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@ -605,93 +606,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type.begins_with("$_DFF_"))
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{
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std::string reg_name = cellname(cell);
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bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
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if (!out_is_reg_wire) {
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f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
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dump_reg_init(f, cell->getPort(ID::Q));
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f << ";\n";
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}
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dump_attributes(f, indent, cell->attributes);
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f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", cell->type[6] == 'P' ? "pos" : "neg");
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dump_sigspec(f, cell->getPort(ID::C));
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if (cell->type[7] != '_') {
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f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
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dump_sigspec(f, cell->getPort(ID::R));
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}
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f << stringf(")\n");
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if (cell->type[7] != '_') {
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f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
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dump_sigspec(f, cell->getPort(ID::R));
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f << stringf(")\n");
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f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
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f << stringf("%s" " else\n", indent.c_str());
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}
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f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str());
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dump_cell_expr_port(f, cell, "D", false);
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f << stringf(";\n");
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if (!out_is_reg_wire) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort(ID::Q));
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f << stringf(" = %s;\n", reg_name.c_str());
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}
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return true;
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}
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if (cell->type.begins_with("$_DFFSR_"))
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{
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char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
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std::string reg_name = cellname(cell);
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bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
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if (!out_is_reg_wire) {
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f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
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dump_reg_init(f, cell->getPort(ID::Q));
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f << ";\n";
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}
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dump_attributes(f, indent, cell->attributes);
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f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", pol_c == 'P' ? "pos" : "neg");
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dump_sigspec(f, cell->getPort(ID::C));
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f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg");
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dump_sigspec(f, cell->getPort(ID::S));
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f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg");
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dump_sigspec(f, cell->getPort(ID::R));
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f << stringf(")\n");
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f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
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dump_sigspec(f, cell->getPort(ID::R));
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f << stringf(")\n");
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f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str());
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f << stringf("%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!");
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dump_sigspec(f, cell->getPort(ID::S));
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f << stringf(")\n");
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f << stringf("%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str());
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f << stringf("%s" " else\n", indent.c_str());
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f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str());
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dump_cell_expr_port(f, cell, "D", false);
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f << stringf(";\n");
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if (!out_is_reg_wire) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort(ID::Q));
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f << stringf(" = %s;\n", reg_name.c_str());
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}
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return true;
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}
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#define HANDLE_UNIOP(_type, _operator) \
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if (cell->type ==_type) { dump_cell_expr_uniop(f, indent, cell, _operator); return true; }
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#define HANDLE_BINOP(_type, _operator) \
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@ -986,154 +900,151 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == ID($dffsr))
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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{
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SigSpec sig_clk = cell->getPort(ID::CLK);
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SigSpec sig_set = cell->getPort(ID::SET);
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SigSpec sig_clr = cell->getPort(ID::CLR);
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SigSpec sig_d = cell->getPort(ID::D);
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SigSpec sig_q = cell->getPort(ID::Q);
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FfData ff(nullptr, cell);
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int width = cell->parameters[ID::WIDTH].as_int();
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bool pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
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bool pol_set = cell->parameters[ID::SET_POLARITY].as_bool();
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bool pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool();
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// $ff / $_FF_ cell: not supported.
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if (ff.has_d && !ff.has_clk && !ff.has_en)
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return false;
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std::string reg_name = cellname(cell);
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bool out_is_reg_wire = is_reg_wire(sig_q, reg_name);
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bool out_is_reg_wire = is_reg_wire(ff.sig_q, reg_name);
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if (!out_is_reg_wire) {
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f << stringf("%s" "reg [%d:0] %s", indent.c_str(), width-1, reg_name.c_str());
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dump_reg_init(f, sig_q);
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if (ff.width == 1)
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f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
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else
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f << stringf("%s" "reg [%d:0] %s", indent.c_str(), ff.width-1, reg_name.c_str());
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dump_reg_init(f, ff.sig_q);
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f << ";\n";
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}
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for (int i = 0; i < width; i++) {
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f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", pol_clk ? "pos" : "neg");
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dump_sigspec(f, sig_clk);
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f << stringf(", %sedge ", pol_set ? "pos" : "neg");
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dump_sigspec(f, sig_set);
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f << stringf(", %sedge ", pol_clr ? "pos" : "neg");
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dump_sigspec(f, sig_clr);
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f << stringf(")\n");
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// If the FF has CLR/SET inputs, emit every bit slice separately.
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int chunks = ff.has_sr ? ff.width : 1;
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bool chunky = ff.has_sr && ff.width != 1;
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f << stringf("%s" " if (%s", indent.c_str(), pol_clr ? "" : "!");
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dump_sigspec(f, sig_clr);
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f << stringf(") %s[%d] <= 1'b0;\n", reg_name.c_str(), i);
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for (int i = 0; i < chunks; i++)
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{
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SigSpec sig_d;
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Const val_arst, val_srst;
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std::string reg_bit_name;
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if (chunky) {
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reg_bit_name = stringf("%s[%d]", reg_name.c_str(), i);
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if (ff.has_d)
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sig_d = ff.sig_d[i];
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} else {
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reg_bit_name = reg_name;
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if (ff.has_d)
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sig_d = ff.sig_d;
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}
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if (ff.has_arst)
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val_arst = chunky ? ff.val_arst[i] : ff.val_arst;
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if (ff.has_srst)
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val_srst = chunky ? ff.val_srst[i] : ff.val_srst;
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f << stringf("%s" " else if (%s", indent.c_str(), pol_set ? "" : "!");
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dump_sigspec(f, sig_set);
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f << stringf(") %s[%d] <= 1'b1;\n", reg_name.c_str(), i);
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dump_attributes(f, indent, cell->attributes);
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if (ff.has_clk)
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{
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// FFs.
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f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", ff.pol_clk ? "pos" : "neg");
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dump_sigspec(f, ff.sig_clk);
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if (ff.has_sr) {
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f << stringf(", %sedge ", ff.pol_set ? "pos" : "neg");
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dump_sigspec(f, ff.sig_set[i]);
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f << stringf(", %sedge ", ff.pol_clr ? "pos" : "neg");
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dump_sigspec(f, ff.sig_clr[i]);
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} else if (ff.has_arst) {
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f << stringf(", %sedge ", ff.pol_arst ? "pos" : "neg");
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dump_sigspec(f, ff.sig_arst);
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}
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f << stringf(")\n");
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f << stringf("%s" " else %s[%d] <= ", indent.c_str(), reg_name.c_str(), i);
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dump_sigspec(f, sig_d[i]);
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f << stringf(";\n");
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f << stringf("%s" " ", indent.c_str());
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if (ff.has_sr) {
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f << stringf("if (%s", ff.pol_clr ? "" : "!");
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dump_sigspec(f, ff.sig_clr[i]);
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f << stringf(") %s <= 1'b0;\n", reg_bit_name.c_str());
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f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!");
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dump_sigspec(f, ff.sig_set[i]);
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f << stringf(") %s <= 1'b1;\n", reg_bit_name.c_str());
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f << stringf("%s" " else ", indent.c_str());
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} else if (ff.has_arst) {
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f << stringf("if (%s", ff.pol_arst ? "" : "!");
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dump_sigspec(f, ff.sig_arst);
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f << stringf(") %s <= ", reg_bit_name.c_str());
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dump_sigspec(f, val_arst);
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_srst && ff.has_en && ff.ce_over_srst) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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f << stringf(")\n");
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f << stringf("%s" " if (%s", indent.c_str(), ff.pol_srst ? "" : "!");
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dump_sigspec(f, ff.sig_srst);
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f << stringf(") %s <= ", reg_bit_name.c_str());
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dump_sigspec(f, val_srst);
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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} else {
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if (ff.has_srst) {
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f << stringf("if (%s", ff.pol_srst ? "" : "!");
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dump_sigspec(f, ff.sig_srst);
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f << stringf(") %s <= ", reg_bit_name.c_str());
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dump_sigspec(f, val_srst);
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f << stringf(";\n");
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_en) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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f << stringf(") ");
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}
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}
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f << stringf("%s <= ", reg_bit_name.c_str());
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dump_sigspec(f, sig_d);
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f << stringf(";\n");
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}
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else
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{
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// Latches.
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f << stringf("%s" "always%s\n", indent.c_str(), systemverilog ? "_latch" : " @*");
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f << stringf("%s" " ", indent.c_str());
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if (ff.has_sr) {
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f << stringf("if (%s", ff.pol_clr ? "" : "!");
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dump_sigspec(f, ff.sig_clr[i]);
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f << stringf(") %s = 1'b0;\n", reg_bit_name.c_str());
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f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!");
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dump_sigspec(f, ff.sig_set[i]);
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f << stringf(") %s = 1'b1;\n", reg_bit_name.c_str());
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if (ff.has_d)
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f << stringf("%s" " else ", indent.c_str());
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} else if (ff.has_arst) {
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f << stringf("if (%s", ff.pol_arst ? "" : "!");
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dump_sigspec(f, ff.sig_arst);
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f << stringf(") %s = ", reg_bit_name.c_str());
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dump_sigspec(f, val_arst);
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f << stringf(";\n");
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if (ff.has_d)
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f << stringf("%s" " else ", indent.c_str());
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}
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if (ff.has_d) {
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f << stringf("if (%s", ff.pol_en ? "" : "!");
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dump_sigspec(f, ff.sig_en);
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f << stringf(") %s = ", reg_bit_name.c_str());
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dump_sigspec(f, sig_d);
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f << stringf(";\n");
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}
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}
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}
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if (!out_is_reg_wire) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, sig_q);
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f << stringf(" = %s;\n", reg_name.c_str());
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}
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return true;
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}
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if (cell->type.in(ID($dff), ID($adff), ID($dffe)))
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{
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RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
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bool pol_clk, pol_arst = false, pol_en = false;
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sig_clk = cell->getPort(ID::CLK);
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pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
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if (cell->type == ID($adff)) {
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sig_arst = cell->getPort(ID::ARST);
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pol_arst = cell->parameters[ID::ARST_POLARITY].as_bool();
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val_arst = RTLIL::SigSpec(cell->parameters[ID::ARST_VALUE]);
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}
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if (cell->type == ID($dffe)) {
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sig_en = cell->getPort(ID::EN);
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pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
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}
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std::string reg_name = cellname(cell);
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bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
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if (!out_is_reg_wire) {
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f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
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dump_reg_init(f, cell->getPort(ID::Q));
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f << ";\n";
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}
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f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", pol_clk ? "pos" : "neg");
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dump_sigspec(f, sig_clk);
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if (cell->type == ID($adff)) {
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f << stringf(" or %sedge ", pol_arst ? "pos" : "neg");
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dump_sigspec(f, sig_arst);
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}
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f << stringf(")\n");
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if (cell->type == ID($adff)) {
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f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!");
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dump_sigspec(f, sig_arst);
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f << stringf(")\n");
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f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str());
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dump_sigspec(f, val_arst);
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f << stringf(";\n");
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f << stringf("%s" " else\n", indent.c_str());
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}
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if (cell->type == ID($dffe)) {
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f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
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dump_sigspec(f, sig_en);
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f << stringf(")\n");
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}
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f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str());
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dump_cell_expr_port(f, cell, "D", false);
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f << stringf(";\n");
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if (!out_is_reg_wire) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort(ID::Q));
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f << stringf(" = %s;\n", reg_name.c_str());
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}
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return true;
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}
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if (cell->type == ID($dlatch))
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{
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RTLIL::SigSpec sig_en;
|
||||
bool pol_en = false;
|
||||
|
||||
sig_en = cell->getPort(ID::EN);
|
||||
pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
|
||||
|
||||
std::string reg_name = cellname(cell);
|
||||
bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
|
||||
|
||||
if (!out_is_reg_wire) {
|
||||
f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
|
||||
dump_reg_init(f, cell->getPort(ID::Q));
|
||||
f << ";\n";
|
||||
}
|
||||
|
||||
f << stringf("%s" "always%s\n", indent.c_str(), systemverilog ? "_latch" : " @*");
|
||||
|
||||
f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
|
||||
dump_sigspec(f, sig_en);
|
||||
f << stringf(")\n");
|
||||
|
||||
f << stringf("%s" " %s = ", indent.c_str(), reg_name.c_str());
|
||||
dump_cell_expr_port(f, cell, "D", false);
|
||||
f << stringf(";\n");
|
||||
|
||||
if (!out_is_reg_wire) {
|
||||
f << stringf("%s" "assign ", indent.c_str());
|
||||
dump_sigspec(f, cell->getPort(ID::Q));
|
||||
dump_sigspec(f, ff.sig_q);
|
||||
f << stringf(" = %s;\n", reg_name.c_str());
|
||||
}
|
||||
|
||||
|
|
@ -1528,8 +1439,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
|
|||
return true;
|
||||
}
|
||||
|
||||
// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
|
||||
// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
|
||||
// FIXME: $memrd, $memwr, $fsm
|
||||
|
||||
return false;
|
||||
}
|
||||
|
|
@ -1602,7 +1512,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
|
|||
}
|
||||
}
|
||||
|
||||
if (siminit && reg_ct.count(cell->type) && cell->hasPort(ID::Q)) {
|
||||
if (siminit && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) {
|
||||
std::stringstream ss;
|
||||
dump_reg_init(ss, cell->getPort(ID::Q));
|
||||
if (!ss.str().empty()) {
|
||||
|
|
@ -1812,7 +1722,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
|
|||
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (!reg_ct.count(cell->type) || !cell->hasPort(ID::Q))
|
||||
if (!RTLIL::builtin_ff_cell_types().count(cell->type) || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_)))
|
||||
continue;
|
||||
|
||||
RTLIL::SigSpec sig = cell->getPort(ID::Q);
|
||||
|
|
@ -1984,33 +1894,6 @@ struct VerilogBackend : public Backend {
|
|||
|
||||
auto_name_map.clear();
|
||||
reg_wires.clear();
|
||||
reg_ct.clear();
|
||||
|
||||
reg_ct.insert(ID($dff));
|
||||
reg_ct.insert(ID($adff));
|
||||
reg_ct.insert(ID($dffe));
|
||||
reg_ct.insert(ID($dlatch));
|
||||
|
||||
reg_ct.insert(ID($_DFF_N_));
|
||||
reg_ct.insert(ID($_DFF_P_));
|
||||
|
||||
reg_ct.insert(ID($_DFF_NN0_));
|
||||
reg_ct.insert(ID($_DFF_NN1_));
|
||||
reg_ct.insert(ID($_DFF_NP0_));
|
||||
reg_ct.insert(ID($_DFF_NP1_));
|
||||
reg_ct.insert(ID($_DFF_PN0_));
|
||||
reg_ct.insert(ID($_DFF_PN1_));
|
||||
reg_ct.insert(ID($_DFF_PP0_));
|
||||
reg_ct.insert(ID($_DFF_PP1_));
|
||||
|
||||
reg_ct.insert(ID($_DFFSR_NNN_));
|
||||
reg_ct.insert(ID($_DFFSR_NNP_));
|
||||
reg_ct.insert(ID($_DFFSR_NPN_));
|
||||
reg_ct.insert(ID($_DFFSR_NPP_));
|
||||
reg_ct.insert(ID($_DFFSR_PNN_));
|
||||
reg_ct.insert(ID($_DFFSR_PNP_));
|
||||
reg_ct.insert(ID($_DFFSR_PPN_));
|
||||
reg_ct.insert(ID($_DFFSR_PPP_));
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
|
|
@ -2107,7 +1990,6 @@ struct VerilogBackend : public Backend {
|
|||
|
||||
auto_name_map.clear();
|
||||
reg_wires.clear();
|
||||
reg_ct.clear();
|
||||
}
|
||||
} VerilogBackend;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue