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Add opt_dff pass.
This commit is contained in:
Marcelina Kościelnicka
parent
8fd43515c5
commit
af6623ebb8
12 changed files with 1790 additions and 3 deletions
101
tests/opt/opt_dff_arst.ys
Normal file
101
tests/opt/opt_dff_arst.ys
Normal file
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### Always-active ARST removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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output [11:0] Q;
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input ARST;
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input EN;
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .ARST(1'b1), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .ARST(1'b0), .EN(EN), .D(D), .Q(Q[3:2]));
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$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.EN(EN), .ARST(1'b1), .D(D), .Q(Q[5:4]));
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .ARST(1'bx), .D(D), .Q(Q[7:6]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .ARST(1'bx), .EN(EN), .D(D), .Q(Q[9:8]));
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$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff5 (.EN(EN), .ARST(1'bx), .D(D), .Q(Q[11:10]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:*
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design -load orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$adlatch
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:*
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 2 t:$_DFF_???_
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select -assert-count 2 t:$_DFFE_????_
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select -assert-count 2 t:$_DLATCH_???_
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design -reset
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### Never-active ARST removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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output [5:0] Q;
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input ARST;
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input EN;
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .ARST(1'b0), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .ARST(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
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$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.EN(EN), .ARST(1'b0), .D(D), .Q(Q[5:4]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:$adff
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select -assert-none t:$adffe
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select -assert-none t:$adlatch
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select -assert-count 1 t:$dff
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select -assert-count 1 t:$dffe
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select -assert-count 1 t:$dlatch
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:$_DFF_???_
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select -assert-none t:$_DFFE_????_
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select -assert-none t:$_DLATCH_???_
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 2 t:$_DFFE_PP_
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select -assert-count 2 t:$_DLATCH_P_
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design -reset
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45
tests/opt/opt_dff_clk.ys
Normal file
45
tests/opt/opt_dff_clk.ys
Normal file
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@ -0,0 +1,45 @@
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### Never-toggling CLK removal.
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read_verilog -icells <<EOT
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module top(...);
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input EN;
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input [1:0] D;
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(* init = 18'h15555 *)
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output [17:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(1'b0), .D(D), .Q(Q[1:0]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(1'bx), .ARST(ARST), .D(D), .Q(Q[5:4]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(1'b0), .EN(EN), .ARST(ARST), .D(D), .Q(Q[7:6]));
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(1'b1), .SRST(SRST), .D(D), .Q(Q[9:8]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(1'bx), .EN(EN), .SRST(SRST), .D(D), .Q(Q[11:10]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(1'bx), .EN(EN), .SRST(SRST), .D(D), .Q(Q[13:12]));
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$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(1'bx), .EN(EN), .SET(SET), .CLR(CLR), .D(D), .Q(Q[17:16]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 2 t:$dlatch
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select -assert-count 2 t:$sr
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select -assert-none t:$dlatch t:$sr %% %n t:* %i
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 4 t:$_DLATCH_?_
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select -assert-count 4 t:$_SR_??_
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select -assert-none t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
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49
tests/opt/opt_dff_const.ys
Normal file
49
tests/opt/opt_dff_const.ys
Normal file
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@ -0,0 +1,49 @@
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### Replace FFs with a const.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input EN;
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(* init=84'haaaaaaaaaaaaaaaaaaaaa *)
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output [83:0] Q;
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input SRST;
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input ARST;
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input [3:0] CLR;
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input [3:0] SET;
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$dff #(.CLK_POLARITY(1'b1), .WIDTH(4)) ff0 (.CLK(CLK), .D(4'hc), .Q(Q[3:0]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(4)) ff1 (.CLK(CLK), .EN(EN), .D(4'hc), .Q(Q[7:4]));
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff2 (.CLK(CLK), .ARST(ARST), .D(8'hcc), .Q(Q[15:8]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(8'hcc), .Q(Q[23:16]));
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff4 (.CLK(CLK), .SRST(SRST), .D(8'hcc), .Q(Q[31:24]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(8'hcc), .Q(Q[39:32]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(8'hcc), .Q(Q[47:40]));
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$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(8)) ff7 (.CLK(CLK), .SET({SET, 4'hf}), .CLR({4'h0, CLR}), .D(8'hcc), .Q(Q[55:48]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b0), .SET_POLARITY(1'b1), .WIDTH(8)) ff8 (.CLK(CLK), .EN(EN), .SET({SET, 4'h0}), .CLR({4'hf, CLR}), .D(8'hcc), .Q(Q[63:56]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(4)) ff9 (.EN(EN), .D(4'hc), .Q(Q[67:64]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff10 (.EN(EN), .ARST(ARST), .D(8'hcc), .Q(Q[75:68]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(8)) ff11 (.EN(EN), .SET({SET, 4'h0}), .CLR({4'h0, CLR}), .D(8'hcc), .Q(Q[83:76]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 1 t:$adff r:WIDTH=6 %i
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select -assert-count 1 t:$adffe r:WIDTH=6 %i
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select -assert-count 1 t:$sdff r:WIDTH=6 %i
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select -assert-count 1 t:$sdffe r:WIDTH=6 %i
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select -assert-count 1 t:$sdffce r:WIDTH=6 %i
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select -assert-count 1 t:$dffsr r:WIDTH=6 %i
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select -assert-count 1 t:$dffsre r:WIDTH=6 %i
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select -assert-count 1 t:$dlatch r:WIDTH=2 %i
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select -assert-count 1 t:$adlatch r:WIDTH=6 %i
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select -assert-count 1 t:$dlatchsr r:WIDTH=6 %i
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157
tests/opt/opt_dff_en.ys
Normal file
157
tests/opt/opt_dff_en.ys
Normal file
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@ -0,0 +1,157 @@
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### Always-active EN removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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output [15:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b1), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b0), .ARST(ARST), .D(D), .Q(Q[3:2]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[5:4]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[7:6]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b1), .D(D), .Q(Q[11:10]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b0), .ARST(ARST), .D(D), .Q(Q[13:12]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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endmodule
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EOT
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design -save orig
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# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
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delete top/ff6 top/ff7
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equiv_opt -undef -assert -multiclock opt_dff
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design -load orig
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delete top/ff6 top/ff7
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load orig
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opt_dff
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select -assert-count 0 t:$dffe
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select -assert-count 0 t:$adffe
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select -assert-count 0 t:$sdffe
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select -assert-count 0 t:$sdffce
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select -assert-count 0 t:$dffsre
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$adlatch
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select -assert-count 0 t:$dlatchsr
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select -assert-count 1 t:$dff
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select -assert-count 2 t:$sdff
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$dffsr
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design -load orig
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simplemap
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opt_dff
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select -assert-count 0 t:$_DFFE_*
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select -assert-count 0 t:$_SDFFE_*
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select -assert-count 0 t:$_SDFFCE_*
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select -assert-count 0 t:$_DFFSRE_*
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select -assert-count 0 t:$_DLATCH*
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 4 t:$_SDFF_PP?_
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select -assert-count 2 t:$_DFF_PP?_
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select -assert-count 2 t:$_DFFSR_PNP_
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design -reset
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### Never-active EN removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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(* init = 32'h55555555 *)
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output [31:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b0), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b1), .ARST(ARST), .D(D), .Q(Q[3:2]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[5:4]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[7:6]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b0), .D(D), .Q(Q[11:10]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b1), .ARST(ARST), .D(D), .Q(Q[13:12]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff8 (.CLK(CLK), .EN(1'bx), .D(D), .Q(Q[17:16]));
|
||||
$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff9 (.CLK(CLK), .EN(1'bx), .ARST(ARST), .D(D), .Q(Q[19:18]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff10 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[21:20]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff11 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[23:22]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff12 (.CLK(CLK), .EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[25:24]));
|
||||
|
||||
$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff13 (.EN(1'bx), .D(D), .Q(Q[27:26]));
|
||||
$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff14 (.EN(1'bx), .ARST(ARST), .D(D), .Q(Q[29:28]));
|
||||
$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff15 (.EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[31:30]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$dffe
|
||||
select -assert-count 4 t:$dlatch
|
||||
select -assert-count 4 t:$sr
|
||||
select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$dffe
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$sdffe
|
||||
select -assert-count 1 t:$sdffce
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 3 t:$dlatch
|
||||
select -assert-count 1 t:$adlatch
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 2 t:$sr
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-count 4 t:$_DFFE_??_
|
||||
select -assert-count 8 t:$_DLATCH_?_
|
||||
select -assert-count 8 t:$_SR_??_
|
||||
select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 4 t:$_DFFE_??_
|
||||
select -assert-count 2 t:$_DFFE_????_
|
||||
select -assert-count 2 t:$_SDFFE_????_
|
||||
select -assert-count 2 t:$_SDFFCE_????_
|
||||
select -assert-count 2 t:$_DFFSRE_????_
|
||||
select -assert-count 6 t:$_DLATCH_?_
|
||||
select -assert-count 2 t:$_DLATCH_???_
|
||||
select -assert-count 2 t:$_DLATCHSR_???_
|
||||
select -assert-count 4 t:$_SR_??_
|
||||
86
tests/opt/opt_dff_mux.ys
Normal file
86
tests/opt/opt_dff_mux.ys
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
### CE and SRST matching.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input NE, NS;
|
||||
input EN;
|
||||
output [23:0] Q;
|
||||
input [23:0] D;
|
||||
input SRST;
|
||||
input ARST;
|
||||
input [1:0] CLR;
|
||||
input [1:0] SET;
|
||||
|
||||
$dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .D(NS ? 2'h2 : NE ? D[1:0] : Q[1:0]), .Q(Q[1:0]));
|
||||
$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(CLK), .EN(EN), .D(NS ? 2'h2 : NE ? D[3:2] : Q[3:2]), .Q(Q[3:2]));
|
||||
$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .ARST(ARST), .D(NS ? 2'h2 : NE ? D[5:4] : Q[5:4]), .Q(Q[5:4]));
|
||||
$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(NS ? 2'h2 : NE ? D[7:6] : Q[7:6]), .Q(Q[7:6]));
|
||||
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[9:8] : Q[9:8]), .Q(Q[9:8]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[11:10] : Q[11:10]), .Q(Q[11:10]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[13:12] : Q[13:12]), .Q(Q[13:12]));
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(NS ? 2'h2 : NE ? D[15:14] : Q[15:14]), .Q(Q[15:14]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(NS ? 2'h2 : NE ? D[17:16] : Q[17:16]), .Q(Q[17:16]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 0 t:$dff
|
||||
select -assert-count 0 t:$dffe
|
||||
select -assert-count 0 t:$adff
|
||||
select -assert-count 2 t:$adffe
|
||||
select -assert-count 0 t:$dffsr
|
||||
select -assert-count 2 t:$dffsre
|
||||
select -assert-count 0 t:$sdff
|
||||
select -assert-count 3 t:$sdffe
|
||||
select -assert-count 2 t:$sdffce
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -nodffe -nosdff
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 1 t:$dff
|
||||
select -assert-count 1 t:$dffe
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 1 t:$sdff
|
||||
select -assert-count 1 t:$sdffe
|
||||
select -assert-count 1 t:$sdffce
|
||||
equiv_opt -undef -assert -multiclock opt_dff -nodffe
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 0 t:$dff
|
||||
select -assert-count 0 t:$dffe
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 2 t:$sdff
|
||||
select -assert-count 1 t:$sdffe
|
||||
select -assert-count 2 t:$sdffce
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -nosdff
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 0 t:$dff
|
||||
select -assert-count 2 t:$dffe
|
||||
select -assert-count 0 t:$adff
|
||||
select -assert-count 2 t:$adffe
|
||||
select -assert-count 0 t:$dffsr
|
||||
select -assert-count 2 t:$dffsre
|
||||
select -assert-count 0 t:$sdff
|
||||
select -assert-count 2 t:$sdffe
|
||||
select -assert-count 1 t:$sdffce
|
||||
56
tests/opt/opt_dff_qd.ys
Normal file
56
tests/opt/opt_dff_qd.ys
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
### Q = D case.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input EN;
|
||||
(* init = 24'h555555 *)
|
||||
output [23:0] Q;
|
||||
input SRST;
|
||||
input ARST;
|
||||
input [1:0] CLR;
|
||||
input [1:0] SET;
|
||||
|
||||
$dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .D(Q[1:0]), .Q(Q[1:0]));
|
||||
$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(CLK), .EN(EN), .D(Q[3:2]), .Q(Q[3:2]));
|
||||
$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .ARST(ARST), .D(Q[5:4]), .Q(Q[5:4]));
|
||||
$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(Q[7:6]), .Q(Q[7:6]));
|
||||
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(SRST), .D(Q[9:8]), .Q(Q[9:8]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(Q[11:10]), .Q(Q[11:10]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(Q[13:12]), .Q(Q[13:12]));
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(Q[15:14]), .Q(Q[15:14]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(Q[17:16]), .Q(Q[17:16]));
|
||||
|
||||
$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff9 (.EN(EN), .D(Q[19:18]), .Q(Q[19:18]));
|
||||
$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff10 (.EN(EN), .ARST(ARST), .D(Q[21:20]), .Q(Q[21:20]));
|
||||
$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff11 (.EN(EN), .SET(SET), .CLR(CLR), .D(Q[23:22]), .Q(Q[23:22]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
|
||||
delete top/ff10 top/ff11
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
|
||||
design -load orig
|
||||
opt_dff -keepdc
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 3 t:$dffe
|
||||
select -assert-count 3 t:$dlatch
|
||||
select -assert-count 3 t:$sr
|
||||
select -assert-none t:$and t:$dffe t:$dlatch t:$sr %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
opt_dff -keepdc
|
||||
select -assert-count 2 t:$_AND_
|
||||
select -assert-count 6 t:$_DFFE_??_
|
||||
select -assert-count 6 t:$_DLATCH_?_
|
||||
select -assert-count 6 t:$_SR_??_
|
||||
select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
|
||||
|
||||
304
tests/opt/opt_dff_sr.ys
Normal file
304
tests/opt/opt_dff_sr.ys
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
### Always-active SET/CLR removal.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input CLR;
|
||||
input SET;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsr r:WIDTH=2 %i
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 1 t:$dffsre r:WIDTH=2 %i
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 1 t:$dlatchsr r:WIDTH=2 %i
|
||||
select -assert-none t:$sr
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsr r:WIDTH=4 %i
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 1 t:$dffsre r:WIDTH=4 %i
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 1 t:$dlatchsr r:WIDTH=4 %i
|
||||
select -assert-count 1 t:$sr
|
||||
select -assert-count 1 t:$sr r:WIDTH=4 %i
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$_DFF_PP0_
|
||||
select -assert-count 1 t:$_DFF_PP1_
|
||||
select -assert-count 1 t:$_DFFE_PN0P_
|
||||
select -assert-count 1 t:$_DFFE_PN1P_
|
||||
select -assert-count 1 t:$_DLATCH_PP0_
|
||||
select -assert-count 1 t:$_DLATCH_PN1_
|
||||
select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_NOT_ %% %n t:* %i
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$_DFF_PP0_
|
||||
select -assert-count 1 t:$_DFF_PP1_
|
||||
select -assert-count 2 t:$_DFFSR_PPP_
|
||||
select -assert-count 1 t:$_DFFE_PN0P_
|
||||
select -assert-count 1 t:$_DFFE_PN1P_
|
||||
select -assert-count 2 t:$_DFFSRE_PNNP_
|
||||
select -assert-count 1 t:$_DLATCH_PP0_
|
||||
select -assert-count 1 t:$_DLATCH_PN1_
|
||||
select -assert-count 2 t:$_DLATCHSR_PNP_
|
||||
select -assert-count 1 t:$_DLATCH_P_
|
||||
select -assert-count 1 t:$_DLATCH_N_
|
||||
select -assert-count 2 t:$_SR_PN_
|
||||
select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFSR_PPP_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DFFSRE_PNNP_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_DLATCHSR_PNP_ t:$_NOT_ t:$_DLATCH_N_ t:$_DLATCH_P_ t:$_SR_PN_ %% %n t:* %i
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
|
||||
### Never-active CLR removal.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input CLR;
|
||||
input SET;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({6{SET}}), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({6{SET}}), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({6{SET}}), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({6{SET}}), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$dffsr
|
||||
select -assert-count 0 t:$dffsre
|
||||
select -assert-count 0 t:$dlatchsr
|
||||
select -assert-count 0 t:$sr
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$adlatch
|
||||
select -assert-count 1 t:$dlatch
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
|
||||
### Never-active CLR removal (not applicable).
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input CLR;
|
||||
input SET;
|
||||
input ALT;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({{5{SET}}, ALT}), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({{5{SET}}, ALT}), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 1 t:$sr
|
||||
select -assert-count 0 t:$adff
|
||||
select -assert-count 0 t:$adffe
|
||||
select -assert-count 0 t:$adlatch
|
||||
select -assert-count 0 t:$dlatch
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$_DFFSR_*
|
||||
select -assert-count 0 t:$_DFFSRE_*
|
||||
select -assert-count 0 t:$_DLATCHSR_*
|
||||
select -assert-count 0 t:$_SR_*
|
||||
select -assert-count 6 t:$_DFF_PP1_
|
||||
select -assert-count 6 t:$_DFFE_PN1P_
|
||||
select -assert-count 6 t:$_DLATCH_PN1_
|
||||
select -assert-count 6 t:$_DLATCH_P_
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
|
||||
### Never-active SET removal.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input CLR;
|
||||
input SET;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({6{CLR}}), .SET(6'h00), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({6{CLR}}), .SET(6'h00), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$dffsr
|
||||
select -assert-count 0 t:$dffsre
|
||||
select -assert-count 0 t:$dlatchsr
|
||||
select -assert-count 0 t:$sr
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$adlatch
|
||||
select -assert-count 1 t:$dlatch
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
|
||||
### Never-active CLR removal (not applicable).
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input CLR;
|
||||
input SET;
|
||||
input ALT;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({{5{CLR}}, ALT}), .SET(6'h00), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({{5{CLR}}, ALT}), .SET(6'h00), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dffsr
|
||||
select -assert-count 1 t:$dffsre
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 1 t:$sr
|
||||
select -assert-count 0 t:$adff
|
||||
select -assert-count 0 t:$adffe
|
||||
select -assert-count 0 t:$adlatch
|
||||
select -assert-count 0 t:$dlatch
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$_DFFSR_*
|
||||
select -assert-count 0 t:$_DFFSRE_*
|
||||
select -assert-count 0 t:$_DLATCHSR_*
|
||||
select -assert-count 0 t:$_SR_*
|
||||
select -assert-count 6 t:$_DFF_PP0_
|
||||
select -assert-count 6 t:$_DFFE_PN0P_
|
||||
select -assert-count 6 t:$_DLATCH_PP0_
|
||||
select -assert-count 6 t:$_DLATCH_N_
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
|
||||
### SET/CLR merge into ARST.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [5:0] D;
|
||||
output [23:0] Q;
|
||||
input ARST;
|
||||
input EN;
|
||||
|
||||
$dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({ARST, 5'h00}), .SET({1'b0, {5{ARST}}}), .D(D), .Q(Q[5:0]));
|
||||
$dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({ARST, 5'h1f}), .SET({1'b1, {5{ARST}}}), .Q(Q[11:6]));
|
||||
$dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({ARST, 5'h00}), .SET({1'b1, {5{ARST}}}), .Q(Q[17:12]));
|
||||
$sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({ARST, 5'h1f}), .SET({1'b0, {5{ARST}}}), .Q(Q[23:18]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$dffsr
|
||||
select -assert-count 0 t:$dffsre
|
||||
select -assert-count 1 t:$dlatchsr
|
||||
select -assert-count 1 t:$sr
|
||||
select -assert-count 1 t:$adff
|
||||
select -assert-count 1 t:$adff r:ARST_VALUE=6'h1f %i
|
||||
select -assert-count 1 t:$adffe
|
||||
select -assert-count 1 t:$adffe r:ARST_VALUE=6'h1f %i
|
||||
select -assert-count 0 t:$adlatch
|
||||
select -assert-count 0 t:$dlatch
|
||||
113
tests/opt/opt_dff_srst.ys
Normal file
113
tests/opt/opt_dff_srst.ys
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
### Always-active SRST removal.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [1:0] D;
|
||||
(* init=12'h555 *)
|
||||
output [11:0] Q;
|
||||
input SRST;
|
||||
input EN;
|
||||
|
||||
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b1), .D(D), .Q(Q[1:0]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[3:2]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[5:4]));
|
||||
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .SRST(1'bx), .D(D), .Q(Q[7:6]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[9:8]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[11:10]));
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-count 0 t:$sdff
|
||||
select -assert-count 0 t:$sdffe
|
||||
select -assert-count 0 t:$sdffce
|
||||
select -assert-count 4 t:$dff
|
||||
select -assert-count 2 t:$dffe
|
||||
|
||||
design -load orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$sdff
|
||||
select -assert-count 1 t:$sdffe
|
||||
select -assert-count 1 t:$sdffce
|
||||
select -assert-count 2 t:$dff
|
||||
select -assert-count 1 t:$dffe
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-none t:$_SDFF_???_
|
||||
select -assert-none t:$_SDFFE_????_
|
||||
select -assert-none t:$_SDFFCE_????_
|
||||
select -assert-count 8 t:$_DFF_?_
|
||||
select -assert-count 4 t:$_DFFE_??_
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$_SDFF_???_
|
||||
select -assert-count 2 t:$_SDFFE_????_
|
||||
select -assert-count 2 t:$_SDFFCE_????_
|
||||
select -assert-count 4 t:$_DFF_?_
|
||||
select -assert-count 2 t:$_DFFE_??_
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
### Never-active SRST removal.
|
||||
|
||||
read_verilog -icells <<EOT
|
||||
|
||||
module top(...);
|
||||
|
||||
input CLK;
|
||||
input [1:0] D;
|
||||
output [5:0] Q;
|
||||
input SRST;
|
||||
input EN;
|
||||
|
||||
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b0), .D(D), .Q(Q[1:0]));
|
||||
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
|
||||
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[5:4]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save orig
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-none t:$sdff
|
||||
select -assert-none t:$sdffe
|
||||
select -assert-none t:$sdffce
|
||||
select -assert-count 1 t:$dff
|
||||
select -assert-count 2 t:$dffe
|
||||
|
||||
design -load orig
|
||||
simplemap
|
||||
|
||||
equiv_opt -undef -assert -multiclock opt_dff
|
||||
design -load postopt
|
||||
select -assert-none t:$_SDFF_???_
|
||||
select -assert-none t:$_SDFFE_????_
|
||||
select -assert-none t:$_SDFFCE_????_
|
||||
select -assert-count 2 t:$_DFF_P_
|
||||
select -assert-count 4 t:$_DFFE_PP_
|
||||
|
||||
design -reset
|
||||
|
||||
|
|
@ -4,7 +4,7 @@ design -stash gold
|
|||
|
||||
read_verilog -icells opt_rmdff.v
|
||||
proc
|
||||
opt_rmdff
|
||||
opt_dff
|
||||
|
||||
select -assert-count 0 c:remove*
|
||||
select -assert-min 7 c:keep*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
read_verilog opt_rmdff_sat.v
|
||||
prep -flatten
|
||||
opt_rmdff -sat
|
||||
synth
|
||||
opt_dff -sat -nosdff
|
||||
simplemap
|
||||
select -assert-count 5 t:$_DFF_P_
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue