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https://github.com/YosysHQ/yosys
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Add support for RSTP
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parent
c6df55a9e7
commit
af147d1430
2 changed files with 70 additions and 26 deletions
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@ -273,7 +273,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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log("ffPmux: %s\n", log_id(st.ffPmux, "--"));
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log("ffPcemux: %s\n", log_id(st.ffPcemux, "--"));
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log("ffPrstmux: %s\n", log_id(st.ffPrstmux, "--"));
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#endif
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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@ -431,10 +432,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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pm.autoremove(st.ffM);
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}
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if (st.ffP) {
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if (st.ffPmux) {
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SigSpec S = st.ffPmux->getPort("\\S");
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if (st.ffPrstmux) {
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SigSpec S = st.ffPrstmux->getPort("\\S");
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cell->setPort("\\RSTP", st.ffPrstpol ? S : pm.module->Not(NEW_ID, S));
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st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\RSTP", State::S1);
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if (st.ffPcemux) {
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SigSpec S = st.ffPcemux->getPort("\\S");
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cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));
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st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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st.ffPcemux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\CEP", State::S1);
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