From ade89324685c26134da2d2f619a071c02fb7e8c4 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 21 Jul 2026 19:20:42 +0200
Subject: [PATCH] rtlil: register a cloned cell's ports with the signorm index

---
 kernel/rtlil.cc | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5ef27ffe9..715db0c15 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3819,14 +3819,17 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
 		type = this->design->twines.copy_from(src_design->twines, other->type_impl);
 
 	RTLIL::Cell *cell = addCell(name, type);
-	if (cross_pool) {
-		for (auto &c : other->connections_)
-			cell->connections_[this->design->twines.copy_from(src_design->twines, c.first)] = c.second;
-	} else {
-		cell->connections_ = other->connections_;
-	}
 	cell->parameters = other->parameters;
 	cell->attributes = other->attributes;
+
+	bool indexed = signorm_indexed();
+	for (auto &c : other->connections_) {
+		TwineRef port = cross_pool ? this->design->twines.copy_from(src_design->twines, c.first) : c.first;
+		if (indexed)
+			cell->setPort(port, c.second);
+		else
+			cell->connections_[port] = c.second;
+	}
 	if (src_design && this->design)
 		copy_src_into(other, src_design, cell, this->design);
 	return cell;