From add5eba9b2070cbaa3ab937bde27fc94f274519b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 14 Mar 2025 14:08:16 +1300
Subject: [PATCH] Design::selection_stack should never be empty

Add a `log_assert` for it in `Design::check()`.
Remove unneeded checks in other places.
---
 kernel/rtlil.cc          | 14 ++++++++------
 kernel/rtlil.h           | 12 ++++--------
 kernel/yosys.cc          |  2 +-
 passes/cmds/select.cc    |  5 ++---
 passes/techmap/aigmap.cc |  1 -
 5 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f9f4cca4a..6a29c42e7 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1102,6 +1102,7 @@ void RTLIL::Design::sort()
 void RTLIL::Design::check()
 {
 #ifndef NDEBUG
+	log_assert(!selection_stack.empty());
 	for (auto &it : modules_) {
 		log_assert(this == it.second->design);
 		log_assert(it.first == it.second->name);
@@ -1125,8 +1126,6 @@ bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
-	if (selection_stack.size() == 0)
-		return true;
 	return selection().selected_module(mod_name);
 }
 
@@ -1134,8 +1133,6 @@ bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
-	if (selection_stack.size() == 0)
-		return true;
 	return selection().selected_whole_module(mod_name);
 }
 
@@ -1143,8 +1140,6 @@ bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
-	if (selection_stack.size() == 0)
-		return true;
 	return selection().selected_member(mod_name, memb_name);
 }
 
@@ -1182,6 +1177,9 @@ void RTLIL::Design::push_complete_selection()
 void RTLIL::Design::pop_selection()
 {
 	selection_stack.pop_back();
+	// Default to a full_selection if we ran out of stack
+	if (selection_stack.empty())
+		push_full_selection();
 }
 
 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
@@ -2366,6 +2364,10 @@ void RTLIL::Module::check()
 			log_assert(!packed_memids.count(memid));
 			packed_memids.insert(memid);
 		}
+		auto cell_mod = design->module(it.first);
+		if (cell_mod != nullptr) {
+			log_assert(!it.second->get_blackbox_attribute());
+		}
 	}
 
 	for (auto &it : processes) {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d7c860b39..1c7eaec39 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1322,17 +1322,13 @@ struct RTLIL::Design
 	}
 
 	template<typename T1> void select(T1 *module) {
-		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection();
-			sel.select(module);
-		}
+		RTLIL::Selection &sel = selection();
+		sel.select(module);
 	}
 
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
-		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection();
-			sel.select(module, member);
-		}
+		RTLIL::Selection &sel = selection();
+		sel.select(module, member);
 	}
 
 
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 85354c163..37e820060 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -679,7 +679,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
 	str += "yosys";
 	if (!design->selected_active_module.empty())
 		str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
-	if (!design->selection_stack.empty() && !design->full_selection()) {
+	if (!design->full_selection()) {
 		if (design->selected_active_module.empty())
 			str += "*";
 		else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 ||
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index bb1055c67..1ed1987c8 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -715,8 +715,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 
 	if (arg[0] == '%') {
 		if (arg == "%") {
-			if (design->selection_stack.size() > 0)
-				work_stack.push_back(design->selection());
+			work_stack.push_back(design->selection());
 		} else
 		if (arg == "%%") {
 			while (work_stack.size() > 1) {
@@ -1507,7 +1506,7 @@ struct SelectPass : public Pass {
 			work_stack.pop_back();
 		}
 
-		log_assert(design->selection_stack.size() > 0);
+		log_assert(!design->selection_stack.empty());
 
 		if (clear_mode) {
 			design->pop_selection();
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index b51ad912e..19e568a61 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -171,7 +171,6 @@ struct AigmapPass : public Pass {
 				module->remove(cell);
 
 			if (select_mode) {
-				log_assert(!design->selection_stack.empty());
 				RTLIL::Selection& sel = design->selection();
 				sel.selected_members[module->name] = std::move(new_sel);
 			}