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analogdevices: expreso does not care about clock buffers

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This commit is contained in:
Lofty 2025-10-12 11:22:46 +01:00
parent 31605cb006
commit acb06021a8
2 changed files with 0 additions and 72 deletions
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70
techlibs/analogdevices/cells_sim.v
View file

@ -55,68 +55,6 @@ module OUTBUF(
endspecify endspecify
endmodule endmodule
module BUFG(
(* clkbuf_driver *)
output O,
input I);
assign O = I;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11
(I => O) = 96;
endspecify
endmodule
module BUFGCTRL(
(* clkbuf_driver *)
output O,
input I0, input I1,
(* invertible_pin = "IS_S0_INVERTED" *)
input S0,
(* invertible_pin = "IS_S1_INVERTED" *)
input S1,
(* invertible_pin = "IS_CE0_INVERTED" *)
input CE0,
(* invertible_pin = "IS_CE1_INVERTED" *)
input CE1,
(* invertible_pin = "IS_IGNORE0_INVERTED" *)
input IGNORE0,
(* invertible_pin = "IS_IGNORE1_INVERTED" *)
input IGNORE1);
parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
wire S0_true = (S0 ^ IS_S0_INVERTED);
wire S1_true = (S1 ^ IS_S1_INVERTED);
assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule
module BUFHCE(
(* clkbuf_driver *)
output O,
input I,
(* invertible_pin = "IS_CE_INVERTED" *)
input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
endmodule
module INV( module INV(
(* clkbuf_inv = "I" *) (* clkbuf_inv = "I" *)
output O, output O,
@ -386,14 +324,6 @@ module CRY4INIT(
assign CO = CYINIT; assign CO = CYINIT;
endmodule endmodule
module ORCY (output O, input CI, I);
assign O = CI | I;
endmodule
module MULT_AND (output LO, input I0, I1);
assign LO = I0 & I1;
endmodule
// Flip-flops. // Flip-flops.
(* abc9_flop, lib_whitebox *) (* abc9_flop, lib_whitebox *)

2
techlibs/analogdevices/synth_analogdevices.cc
View file

@ -496,8 +496,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
} }
if (check_label("finalize")) { if (check_label("finalize")) {
if (help_mode || !noclkbuf)
run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')");
run("clean"); run("clean");
} }