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https://github.com/YosysHQ/yosys
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analogdevices: prepare for t40lp timings
This commit is contained in:
Lofty
parent
e7cc402b92
commit
31605cb006
2 changed files with 53 additions and 17 deletions
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@ -41,17 +41,6 @@ module INBUF(
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endspecify
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endmodule
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module IBUFG(
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output O,
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(* iopad_external_pin *)
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input I);
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parameter CAPACITANCE = "DONT_CARE";
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parameter IBUF_DELAY_VALUE = "0";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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assign O = I;
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endmodule
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module OUTBUF(
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(* iopad_external_pin *)
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output O,
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@ -134,18 +123,22 @@ module INV(
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input I
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);
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assign O = !I;
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`ifdef t16ffc
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specify
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(I => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=1 *)
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=2 *)
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@ -153,10 +146,12 @@ module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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(I1 => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=3 *)
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@ -165,11 +160,13 @@ module LUT3(output O, input I0, I1, I2);
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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(I1 => O) = 22;
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(I2 => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=4 *)
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@ -179,12 +176,14 @@ module LUT4(output O, input I0, I1, I2, I3);
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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(I1 => O) = 22;
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(I2 => O) = 22;
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(I3 => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=5 *)
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@ -195,6 +194,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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(I1 => O) = 22;
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@ -202,6 +202,7 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
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(I3 => O) = 22;
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(I4 => O) = 22;
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endspecify
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`endif
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endmodule
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(* abc9_lut=6 *)
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@ -213,6 +214,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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`ifdef t16ffc
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specify
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(I0 => O) = 22;
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(I1 => O) = 22;
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@ -221,6 +223,7 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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(I4 => O) = 22;
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(I5 => O) = 22;
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endspecify
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`endif
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endmodule
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module LUT6_D(output O6, output O5, input I0, I1, I2, I3, I4, I5);
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@ -244,6 +247,7 @@ endmodule
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(* abc9_lut=12 *)
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module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
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`ifndef __ICARUS__
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`ifdef t16ffc
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specify
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(I0 => O) = 22 + 63 /* LUTMUX7.I1 */;
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(I1 => O) = 22 + 63 /* LUTMUX7.I1 */;
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@ -254,6 +258,7 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
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(I6 => O) = 0 + 51 /* LUTMUX7.S */;
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endspecify
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`endif
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`endif
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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@ -261,6 +266,7 @@ endmodule
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(* abc9_lut=24 *)
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module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
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`ifndef __ICARUS__
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`ifdef t16ffc
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specify
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(I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
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(I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
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@ -272,26 +278,31 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
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(I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */;
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endspecify
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`endif
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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module LUTMUX7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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`ifdef t16ffc
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specify
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(I0 => O) = 62;
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(I1 => O) = 63;
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(S => O) = 51;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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module LUTMUX8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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`ifdef t16ffc
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specify
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(I0 => O) = 48;
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(I1 => O) = 46;
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(S => O) = 58;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -309,8 +320,8 @@ module CRY4(
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assign CO[1] = S[1] ? CO[0] : DI[1];
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assign CO[2] = S[2] ? CO[1] : DI[2];
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assign CO[3] = S[3] ? CO[2] : DI[3];
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`ifdef t16ffc
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specify
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// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
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(S[0] => O[0]) = 39;
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(CI => O[0]) = 43;
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(DI[0] => O[1]) = 81;
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@ -356,6 +367,7 @@ module CRY4(
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(S[3] => CO[3]) = 81;
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(CI => CO[3]) = 20;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -365,9 +377,11 @@ module CRY4INIT(
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(* abc9_carry *)
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input CYINIT
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);
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`ifdef t16ffc
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specify
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(CYINIT => CO) = 72;
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endspecify
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`endif
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assign CO = CYINIT;
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endmodule
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@ -394,6 +408,7 @@ module FFRE (
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , posedge C, 31);
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$setup(CE, posedge C, 122);
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@ -401,6 +416,7 @@ module FFRE (
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if (R) (posedge C => (Q : 1'b0)) = 280;
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if (!R && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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(* abc9_flop, lib_whitebox *)
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@ -415,6 +431,7 @@ module FFRE_N (
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , negedge C, 31);
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$setup(CE, negedge C, 122);
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@ -422,6 +439,7 @@ module FFRE_N (
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if (R) (negedge C => (Q : 1'b0)) = 280;
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if (!R && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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module FFSE (
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@ -435,6 +453,7 @@ module FFSE (
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , posedge C, 31);
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$setup(CE, posedge C, 122);
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@ -442,6 +461,7 @@ module FFSE (
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if (S) (negedge C => (Q : 1'b1)) = 280;
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if (!S && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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module FFSE_N (
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@ -455,6 +475,7 @@ module FFSE_N (
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , negedge C, 31);
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$setup(CE, negedge C, 122);
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@ -462,6 +483,7 @@ module FFSE_N (
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if (S) (negedge C => (Q : 1'b1)) = 280;
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if (!S && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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module FFCE (
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@ -475,11 +497,13 @@ module FFCE (
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , posedge C, 31);
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$setup(CE , posedge C, 122);
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if (!CLR && CE) (posedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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module FFCE_N (
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@ -493,11 +517,13 @@ module FFCE_N (
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , negedge C, 31);
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$setup(CE , negedge C, 122);
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if (!CLR && CE) (negedge C => (Q : D)) = 280;
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endspecify
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`endif
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endmodule
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module FFPE (
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@ -511,11 +537,13 @@ module FFPE (
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , posedge C, 31);
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$setup(CE , posedge C, 122);
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if (!PRE && CE) (posedge C => (Q : D)) = 291;
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endspecify
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`endif
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endmodule
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module FFPE_N (
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@ -529,11 +557,13 @@ module FFPE_N (
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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`ifdef t16ffc
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specify
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$setup(D , negedge C, 31);
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$setup(CE , negedge C, 122);
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if (!PRE && CE) (negedge C => (Q : D)) = 291;
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endspecify
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`endif
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endmodule
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// LUTRAM.
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@ -554,6 +584,7 @@ module RAMS32X1 (
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reg [31:0] mem = INIT;
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assign O = mem[a];
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef t16ffc
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specify
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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@ -569,6 +600,7 @@ module RAMS32X1 (
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(A4 => O) = 63;
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(posedge WCLK => (O : D)) = 813;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -585,6 +617,7 @@ module RAMS64X1 (
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reg [63:0] mem = INIT;
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assign O = mem[a];
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef t16ffc
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specify
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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@ -602,6 +635,7 @@ module RAMS64X1 (
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(A5 => O) = 64;
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(posedge WCLK => (O : D)) = 762;
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endspecify
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`endif
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endmodule
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// Dual port.
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@ -623,6 +657,7 @@ module RAMD32X1 (
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assign SPO = mem[a];
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assign DPO = mem[dpra];
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef t16ffc
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specify
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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@ -651,6 +686,7 @@ module RAMD32X1 (
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(posedge WCLK => (SPO : D)) = 813;
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(posedge WCLK => (DPO : D)) = 813;
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endspecify
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`endif
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endmodule
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(* abc9_box, lib_whitebox *)
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@ -670,6 +706,7 @@ module RAMD64X1 (
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assign SPO = mem[a];
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assign DPO = mem[dpra];
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always @(posedge WCLK) if (WE) mem[a] <= D;
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`ifdef t16ffc
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specify
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$setup(A0, posedge WCLK, 0);
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$setup(A1, posedge WCLK, 0);
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@ -701,6 +738,7 @@ module RAMD64X1 (
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(posedge WCLK => (SPO : D)) = 762;
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(posedge WCLK => (DPO : D)) = 737;
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endspecify
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`endif
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endmodule
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// Shift registers.
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@ -718,6 +756,7 @@ module SRG16E (
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reg [15:0] r = INIT;
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assign Q = r[{A3,A2,A1,A0}];
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always @(posedge CLK) if (CE) r <= { r[14:0], D };
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`ifdef t16ffc
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specify
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$setup(D , posedge CLK, 173);
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if (CE) (posedge CLK => (Q : D)) = 1472;
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@ -727,6 +766,7 @@ module SRG16E (
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(A2 => Q) = 407;
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(A3 => Q) = 238;
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endspecify
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`endif
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endmodule
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// DSP
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@ -266,12 +266,8 @@ struct SynthAnalogDevicesPass : public ScriptPass
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void script() override
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{
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if (check_label("begin")) {
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std::string read_args;
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read_args += " -lib -specify +/analogdevices/cells_sim.v";
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run("read_verilog" + read_args);
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run(stringf("read_verilog -lib -specify -D %s +/analogdevices/cells_sim.v", tech));
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run("read_verilog -lib +/analogdevices/cells_xtra.v");
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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}
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