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Add equiv_make -norewire

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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-05-04 16:34:34 +02:00
parent 57a22f348c
commit abefba2b58
1 changed files with 11 additions and 1 deletions
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12
passes/equiv/equiv_make.cc
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@ -30,7 +30,7 @@ struct EquivMakeWorker
pool<IdString> wire_names, cell_names;
CellTypes ct;
bool inames;
bool inames, norewire;
vector<string> blacklists;
vector<string> encfiles;
@ -281,6 +281,8 @@ struct EquivMakeWorker
for (auto c : cells_list)
for (auto &conn : c->connections())
if (!ct.cell_output(c->type, conn.first)) {
if (norewire)
continue;
SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig);
if (old_sig != new_sig) {
@ -403,6 +405,9 @@ struct EquivMakePass : public Pass {
log(" -inames\n");
log(" Also match cells and wires with $... names.\n");
log("\n");
log(" -norewire\n");
log(" Do not rewire cell inputs to $equiv outputs.\n");
log("\n");
log(" -blacklist <file>\n");
log(" Do not match cells or signals that match the names in the file.\n");
log("\n");
@ -420,6 +425,7 @@ struct EquivMakePass : public Pass {
EquivMakeWorker worker;
worker.ct.setup(design);
worker.inames = false;
worker.norewire = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -428,6 +434,10 @@ struct EquivMakePass : public Pass {
worker.inames = true;
continue;
}
if (args[argidx] == "-norewire") {
worker.norewire = true;
continue;
}
if (args[argidx] == "-blacklist" && argidx+1 < args.size()) {
worker.blacklists.push_back(args[++argidx]);
continue;