From abefba2b588d4b3e59fb107f7b64a3bc0a57472a Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Tue, 4 May 2021 16:34:34 +0200
Subject: [PATCH] Add equiv_make -norewire

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 passes/equiv/equiv_make.cc | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 4d9e3b71a..237a4f625 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -30,7 +30,7 @@ struct EquivMakeWorker
 	pool<IdString> wire_names, cell_names;
 	CellTypes ct;
 
-	bool inames;
+	bool inames, norewire;
 	vector<string> blacklists;
 	vector<string> encfiles;
 
@@ -281,6 +281,8 @@ struct EquivMakeWorker
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
 			if (!ct.cell_output(c->type, conn.first)) {
+				if (norewire)
+					continue;
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
 				if (old_sig != new_sig) {
@@ -403,6 +405,9 @@ struct EquivMakePass : public Pass {
 		log("    -inames\n");
 		log("        Also match cells and wires with $... names.\n");
 		log("\n");
+		log("    -norewire\n");
+		log("        Do not rewire cell inputs to $equiv outputs.\n");
+		log("\n");
 		log("    -blacklist <file>\n");
 		log("        Do not match cells or signals that match the names in the file.\n");
 		log("\n");
@@ -420,6 +425,7 @@ struct EquivMakePass : public Pass {
 		EquivMakeWorker worker;
 		worker.ct.setup(design);
 		worker.inames = false;
+		worker.norewire = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -428,6 +434,10 @@ struct EquivMakePass : public Pass {
 				worker.inames = true;
 				continue;
 			}
+			if (args[argidx] == "-norewire") {
+				worker.norewire = true;
+				continue;
+			}
 			if (args[argidx] == "-blacklist" && argidx+1 < args.size()) {
 				worker.blacklists.push_back(args[++argidx]);
 				continue;