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Use equiv_opt -nocells to ensure everything is ok since dffs retain their name

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Akash Levy 2025-01-16 19:40:18 -08:00
parent 67a93dc76d
commit ab338b33cb
30 changed files with 201 additions and 201 deletions
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12
tests/opt/opt_dff_arst.ys
View file

@ -24,13 +24,13 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:* select -assert-none t:*
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$adff select -assert-count 1 t:$adff
select -assert-count 1 t:$adffe select -assert-count 1 t:$adffe
@ -39,14 +39,14 @@ select -assert-count 1 t:$adlatch
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:* select -assert-none t:*
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 2 t:$_DFF_???_ select -assert-count 2 t:$_DFF_???_
select -assert-count 2 t:$_DFFE_????_ select -assert-count 2 t:$_DFFE_????_
@ -77,7 +77,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:$adff select -assert-none t:$adff
select -assert-none t:$adffe select -assert-none t:$adffe
@ -89,7 +89,7 @@ select -assert-count 1 t:$dlatch
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:$_DFF_???_ select -assert-none t:$_DFF_???_
select -assert-none t:$_DFFE_????_ select -assert-none t:$_DFFE_????_

4
tests/opt/opt_dff_clk.ys
View file

@ -29,7 +29,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 2 t:$dlatch select -assert-count 2 t:$dlatch
select -assert-count 2 t:$sr select -assert-count 2 t:$sr
@ -38,7 +38,7 @@ select -assert-none t:$dlatch t:$sr %% %n t:* %i
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 4 t:$_DLATCH_?_ select -assert-count 4 t:$_DLATCH_?_
select -assert-count 4 t:$_SR_??_ select -assert-count 4 t:$_SR_??_

2
tests/opt/opt_dff_const.ys
View file

@ -33,7 +33,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$dff r:WIDTH=2 %i
select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 1 t:$dffe r:WIDTH=2 %i

14
tests/opt/opt_dff_dffmux.ys
View file

@ -6,7 +6,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D select -assert-count 0 t:$dffe %% t:* %D
@ -21,7 +21,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
wreduce wreduce
select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 1 t:$dffe r:WIDTH=2 %i
@ -37,7 +37,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D select -assert-count 0 t:$dffe %% t:* %D
@ -52,7 +52,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=4 %i select -assert-count 1 t:$dffe r:WIDTH=4 %i
select -assert-count 0 t:$dffe %% t:* %D select -assert-count 0 t:$dffe %% t:* %D
@ -67,7 +67,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
wreduce wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -86,7 +86,7 @@ endmodule
EOT EOT
proc proc
equiv_opt -assert opt equiv_opt -nocells -assert opt
design -load postopt design -load postopt
wreduce wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -113,7 +113,7 @@ proc
# instead of `sat -tempinduct-baseonly` or # instead of `sat -tempinduct-baseonly` or
# `sat -tempinduct` which is necessary for this # `sat -tempinduct` which is necessary for this
# testcase # testcase
#equiv_opt -assert opt #equiv_opt -nocells -assert opt
design -save gold design -save gold
opt opt

12
tests/opt/opt_dff_en.ys
View file

@ -30,12 +30,12 @@ design -save orig
# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack. # Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
delete top/ff6 top/ff7 delete top/ff6 top/ff7
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load orig design -load orig
delete top/ff6 top/ff7 delete top/ff6 top/ff7
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load orig design -load orig
opt_dff opt_dff
@ -110,7 +110,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 2 t:$dffe select -assert-count 2 t:$dffe
select -assert-count 4 t:$dlatch select -assert-count 4 t:$dlatch
@ -119,7 +119,7 @@ select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 2 t:$dffe select -assert-count 2 t:$dffe
select -assert-count 1 t:$adffe select -assert-count 1 t:$adffe
@ -134,7 +134,7 @@ select -assert-count 2 t:$sr
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 4 t:$_DFFE_??_ select -assert-count 4 t:$_DFFE_??_
select -assert-count 8 t:$_DLATCH_?_ select -assert-count 8 t:$_DLATCH_?_
@ -144,7 +144,7 @@ select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 4 t:$_DFFE_??_ select -assert-count 4 t:$_DFFE_??_
select -assert-count 2 t:$_DFFE_????_ select -assert-count 2 t:$_DFFE_????_

8
tests/opt/opt_dff_mux.ys
View file

@ -30,7 +30,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
clean clean
select -assert-count 0 t:$dff select -assert-count 0 t:$dff
@ -45,7 +45,7 @@ select -assert-count 2 t:$sdffce
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -nodffe -nosdff equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe -nosdff
design -load postopt design -load postopt
clean clean
select -assert-count 1 t:$dff select -assert-count 1 t:$dff
@ -57,7 +57,7 @@ select -assert-count 1 t:$dffsre
select -assert-count 1 t:$sdff select -assert-count 1 t:$sdff
select -assert-count 1 t:$sdffe select -assert-count 1 t:$sdffe
select -assert-count 1 t:$sdffce select -assert-count 1 t:$sdffce
equiv_opt -undef -assert -multiclock opt_dff -nodffe equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe
design -load postopt design -load postopt
clean clean
select -assert-count 0 t:$dff select -assert-count 0 t:$dff
@ -72,7 +72,7 @@ select -assert-count 2 t:$sdffce
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -nosdff equiv_opt -nocells -undef -assert -multiclock opt_dff -nosdff
design -load postopt design -load postopt
clean clean
select -assert-count 0 t:$dff select -assert-count 0 t:$dff

2
tests/opt/opt_dff_qd.ys
View file

@ -29,7 +29,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load orig design -load orig
opt_dff -keepdc opt_dff -keepdc

22
tests/opt/opt_dff_sr.ys
View file

@ -22,7 +22,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr
@ -35,7 +35,7 @@ select -assert-none t:$sr
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr
@ -50,7 +50,7 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 1 t:$_DFF_PP0_ select -assert-count 1 t:$_DFF_PP0_
@ -64,7 +64,7 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$_DFF_PP0_ select -assert-count 1 t:$_DFF_PP0_
@ -109,7 +109,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre select -assert-count 0 t:$dffsre
@ -149,7 +149,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr
select -assert-count 1 t:$dffsre select -assert-count 1 t:$dffsre
@ -163,7 +163,7 @@ select -assert-count 0 t:$dlatch
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 0 t:$_DFFSR_* select -assert-count 0 t:$_DFFSR_*
select -assert-count 0 t:$_DFFSRE_* select -assert-count 0 t:$_DFFSRE_*
@ -202,7 +202,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre select -assert-count 0 t:$dffsre
@ -242,7 +242,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr
select -assert-count 1 t:$dffsre select -assert-count 1 t:$dffsre
@ -256,7 +256,7 @@ select -assert-count 0 t:$dlatch
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 0 t:$_DFFSR_* select -assert-count 0 t:$_DFFSR_*
select -assert-count 0 t:$_DFFSRE_* select -assert-count 0 t:$_DFFSRE_*
@ -294,7 +294,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre select -assert-count 0 t:$dffsre

12
tests/opt/opt_dff_srst.ys
View file

@ -25,7 +25,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-count 0 t:$sdff select -assert-count 0 t:$sdff
select -assert-count 0 t:$sdffe select -assert-count 0 t:$sdffe
@ -35,7 +35,7 @@ select -assert-count 2 t:$dffe
design -load orig design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 1 t:$sdff select -assert-count 1 t:$sdff
select -assert-count 1 t:$sdffe select -assert-count 1 t:$sdffe
@ -46,7 +46,7 @@ select -assert-count 1 t:$dffe
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:$_SDFF_???_ select -assert-none t:$_SDFF_???_
select -assert-none t:$_SDFFE_????_ select -assert-none t:$_SDFFE_????_
@ -57,7 +57,7 @@ select -assert-count 4 t:$_DFFE_??_
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt design -load postopt
select -assert-count 2 t:$_SDFF_???_ select -assert-count 2 t:$_SDFF_???_
select -assert-count 2 t:$_SDFFE_????_ select -assert-count 2 t:$_SDFFE_????_
@ -90,7 +90,7 @@ EOT
design -save orig design -save orig
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:$sdff select -assert-none t:$sdff
select -assert-none t:$sdffe select -assert-none t:$sdffe
@ -101,7 +101,7 @@ select -assert-count 2 t:$dffe
design -load orig design -load orig
simplemap simplemap
equiv_opt -undef -assert -multiclock opt_dff equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt design -load postopt
select -assert-none t:$_SDFF_???_ select -assert-none t:$_SDFF_???_
select -assert-none t:$_SDFFE_????_ select -assert-none t:$_SDFFE_????_

12
tests/techmap/dfflegalize_adff.ys
View file

@ -37,12 +37,12 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs. # Convert everything to ADFFs.

32
tests/techmap/dfflegalize_adff_init.ys
View file

@ -37,22 +37,22 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

4
tests/techmap/dfflegalize_adlatch.ys
View file

@ -21,8 +21,8 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_adlatch_init.ys
View file

@ -21,12 +21,12 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

8
tests/techmap/dfflegalize_aldff.ys
View file

@ -22,10 +22,10 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ALDFFs. # Convert everything to ALDFFs.

16
tests/techmap/dfflegalize_aldff_init.ys
View file

@ -22,14 +22,14 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ALDFFs. # Convert everything to ALDFFs.

22
tests/techmap/dfflegalize_dff.ys
View file

@ -66,17 +66,17 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x
# Convert everything to DFFs. # Convert everything to DFFs.

64
tests/techmap/dfflegalize_dff_init.ys
View file

@ -66,38 +66,38 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1
# Convert everything to DFFs. # Convert everything to DFFs.

8
tests/techmap/dfflegalize_dffsr.ys
View file

@ -24,10 +24,10 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs. # Convert everything to ADFFs.

24
tests/techmap/dfflegalize_dffsr_init.ys
View file

@ -41,18 +41,18 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

10
tests/techmap/dfflegalize_dlatch.ys
View file

@ -8,11 +8,11 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
# Convert everything to DFFs. # Convert everything to DFFs.

8
tests/techmap/dfflegalize_dlatch_const.ys
View file

@ -14,10 +14,10 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

24
tests/techmap/dfflegalize_dlatch_init.ys
View file

@ -8,18 +8,18 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
# Convert everything to DFFs. # Convert everything to DFFs.

4
tests/techmap/dfflegalize_dlatchsr.ys
View file

@ -10,8 +10,8 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_dlatchsr_init.ys
View file

@ -23,12 +23,12 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

6
tests/techmap/dfflegalize_inv.ys
View file

@ -103,7 +103,7 @@ EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
design -load postopt design -load postopt
select -assert-count 51 t:$_NOT_ select -assert-count 51 t:$_NOT_
@ -134,7 +134,7 @@ select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFS
design -load orig design -load orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
design -load postopt design -load postopt
select -assert-count 135 t:$_NOT_ select -assert-count 135 t:$_NOT_
@ -179,7 +179,7 @@ endmodule
EOT EOT
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
design -load postopt design -load postopt
select -assert-count 6 t:$_NOT_ select -assert-count 6 t:$_NOT_

2
tests/techmap/dfflegalize_mince.ys
View file

@ -22,7 +22,7 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
design -load postopt design -load postopt
select -assert-count 4 t:$_DFFE_PP_ select -assert-count 4 t:$_DFFE_PP_

2
tests/techmap/dfflegalize_minsrst.ys
View file

@ -18,7 +18,7 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
design -load postopt design -load postopt
select -assert-count 5 t:$_SDFF_PP0_ select -assert-count 5 t:$_SDFF_PP0_

12
tests/techmap/dfflegalize_sr.ys
View file

@ -9,12 +9,12 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to SRs. # Convert everything to SRs.

24
tests/techmap/dfflegalize_sr_init.ys
View file

@ -21,18 +21,18 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to SRs. # Convert everything to SRs.

8
tests/techmap/zinit.ys
View file

@ -19,7 +19,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock zinit equiv_opt -nocells -assert -multiclock zinit
design -load postopt design -load postopt
select -assert-count 16 t:$_NOT_ select -assert-count 16 t:$_NOT_
@ -52,7 +52,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock zinit equiv_opt -nocells -assert -multiclock zinit
design -load postopt design -load postopt
select -assert-count 0 t:$_NOT_ select -assert-count 0 t:$_NOT_
@ -95,7 +95,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock zinit equiv_opt -nocells -assert -multiclock zinit
design -load postopt design -load postopt
select -assert-count 48 t:$_NOT_ select -assert-count 48 t:$_NOT_
@ -141,7 +141,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock zinit equiv_opt -nocells -assert -multiclock zinit
design -load postopt design -load postopt
select -assert-count 0 t:$_NOT_ select -assert-count 0 t:$_NOT_