From ab338b33cbb2e667fb8d3b470ab30ade60726e3b Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 16 Jan 2025 19:40:18 -0800 Subject: [PATCH] Use equiv_opt -nocells to ensure everything is ok since dffs retain their name --- tests/opt/opt_dff_arst.ys | 12 ++-- tests/opt/opt_dff_clk.ys | 4 +- tests/opt/opt_dff_const.ys | 2 +- tests/opt/opt_dff_dffmux.ys | 14 ++--- tests/opt/opt_dff_en.ys | 12 ++-- tests/opt/opt_dff_mux.ys | 8 +-- tests/opt/opt_dff_qd.ys | 2 +- tests/opt/opt_dff_sr.ys | 22 ++++---- tests/opt/opt_dff_srst.ys | 12 ++-- tests/techmap/dfflegalize_adff.ys | 12 ++-- tests/techmap/dfflegalize_adff_init.ys | 32 +++++------ tests/techmap/dfflegalize_adlatch.ys | 4 +- tests/techmap/dfflegalize_adlatch_init.ys | 12 ++-- tests/techmap/dfflegalize_aldff.ys | 8 +-- tests/techmap/dfflegalize_aldff_init.ys | 16 +++--- tests/techmap/dfflegalize_dff.ys | 22 ++++---- tests/techmap/dfflegalize_dff_init.ys | 64 +++++++++++----------- tests/techmap/dfflegalize_dffsr.ys | 8 +-- tests/techmap/dfflegalize_dffsr_init.ys | 24 ++++---- tests/techmap/dfflegalize_dlatch.ys | 10 ++-- tests/techmap/dfflegalize_dlatch_const.ys | 8 +-- tests/techmap/dfflegalize_dlatch_init.ys | 24 ++++---- tests/techmap/dfflegalize_dlatchsr.ys | 4 +- tests/techmap/dfflegalize_dlatchsr_init.ys | 12 ++-- tests/techmap/dfflegalize_inv.ys | 6 +- tests/techmap/dfflegalize_mince.ys | 2 +- tests/techmap/dfflegalize_minsrst.ys | 2 +- tests/techmap/dfflegalize_sr.ys | 12 ++-- tests/techmap/dfflegalize_sr_init.ys | 24 ++++---- tests/techmap/zinit.ys | 8 +-- 30 files changed, 201 insertions(+), 201 deletions(-) diff --git a/tests/opt/opt_dff_arst.ys b/tests/opt/opt_dff_arst.ys index 2aa3b7a26..c930c5c45 100644 --- a/tests/opt/opt_dff_arst.ys +++ b/tests/opt/opt_dff_arst.ys @@ -24,13 +24,13 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:* design -load orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$adff select -assert-count 1 t:$adffe @@ -39,14 +39,14 @@ select -assert-count 1 t:$adlatch design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:* design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 2 t:$_DFF_???_ select -assert-count 2 t:$_DFFE_????_ @@ -77,7 +77,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:$adff select -assert-none t:$adffe @@ -89,7 +89,7 @@ select -assert-count 1 t:$dlatch design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:$_DFF_???_ select -assert-none t:$_DFFE_????_ diff --git a/tests/opt/opt_dff_clk.ys b/tests/opt/opt_dff_clk.ys index f3aefa406..c112e4de4 100644 --- a/tests/opt/opt_dff_clk.ys +++ b/tests/opt/opt_dff_clk.ys @@ -29,7 +29,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 2 t:$dlatch select -assert-count 2 t:$sr @@ -38,7 +38,7 @@ select -assert-none t:$dlatch t:$sr %% %n t:* %i design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 4 t:$_DLATCH_?_ select -assert-count 4 t:$_SR_??_ diff --git a/tests/opt/opt_dff_const.ys b/tests/opt/opt_dff_const.ys index 6a7dec7fa..98333fc9e 100644 --- a/tests/opt/opt_dff_const.ys +++ b/tests/opt/opt_dff_const.ys @@ -33,7 +33,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$dffe r:WIDTH=2 %i diff --git a/tests/opt/opt_dff_dffmux.ys b/tests/opt/opt_dff_dffmux.ys index 43190cc31..4d71a5a9a 100644 --- a/tests/opt/opt_dff_dffmux.ys +++ b/tests/opt/opt_dff_dffmux.ys @@ -6,7 +6,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 0 t:$dffe %% t:* %D @@ -21,7 +21,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt wreduce select -assert-count 1 t:$dffe r:WIDTH=2 %i @@ -37,7 +37,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt select -assert-count 1 t:$dffe r:WIDTH=2 %i select -assert-count 0 t:$dffe %% t:* %D @@ -52,7 +52,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt select -assert-count 1 t:$dffe r:WIDTH=4 %i select -assert-count 0 t:$dffe %% t:* %D @@ -67,7 +67,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt wreduce select -assert-count 1 t:$sdffe r:WIDTH=2 %i @@ -86,7 +86,7 @@ endmodule EOT proc -equiv_opt -assert opt +equiv_opt -nocells -assert opt design -load postopt wreduce select -assert-count 1 t:$sdffe r:WIDTH=2 %i @@ -113,7 +113,7 @@ proc # instead of `sat -tempinduct-baseonly` or # `sat -tempinduct` which is necessary for this # testcase -#equiv_opt -assert opt +#equiv_opt -nocells -assert opt design -save gold opt diff --git a/tests/opt/opt_dff_en.ys b/tests/opt/opt_dff_en.ys index 9538afcc2..1b1b87433 100644 --- a/tests/opt/opt_dff_en.ys +++ b/tests/opt/opt_dff_en.ys @@ -30,12 +30,12 @@ design -save orig # Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack. delete top/ff6 top/ff7 -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load orig delete top/ff6 top/ff7 simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load orig opt_dff @@ -110,7 +110,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 2 t:$dffe select -assert-count 4 t:$dlatch @@ -119,7 +119,7 @@ select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i design -load orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 2 t:$dffe select -assert-count 1 t:$adffe @@ -134,7 +134,7 @@ select -assert-count 2 t:$sr design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 4 t:$_DFFE_??_ select -assert-count 8 t:$_DLATCH_?_ @@ -144,7 +144,7 @@ select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 4 t:$_DFFE_??_ select -assert-count 2 t:$_DFFE_????_ diff --git a/tests/opt/opt_dff_mux.ys b/tests/opt/opt_dff_mux.ys index f21f9e9b8..7f27f487f 100644 --- a/tests/opt/opt_dff_mux.ys +++ b/tests/opt/opt_dff_mux.ys @@ -30,7 +30,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt clean select -assert-count 0 t:$dff @@ -45,7 +45,7 @@ select -assert-count 2 t:$sdffce design -load orig -equiv_opt -undef -assert -multiclock opt_dff -nodffe -nosdff +equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe -nosdff design -load postopt clean select -assert-count 1 t:$dff @@ -57,7 +57,7 @@ select -assert-count 1 t:$dffsre select -assert-count 1 t:$sdff select -assert-count 1 t:$sdffe select -assert-count 1 t:$sdffce -equiv_opt -undef -assert -multiclock opt_dff -nodffe +equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe design -load postopt clean select -assert-count 0 t:$dff @@ -72,7 +72,7 @@ select -assert-count 2 t:$sdffce design -load orig -equiv_opt -undef -assert -multiclock opt_dff -nosdff +equiv_opt -nocells -undef -assert -multiclock opt_dff -nosdff design -load postopt clean select -assert-count 0 t:$dff diff --git a/tests/opt/opt_dff_qd.ys b/tests/opt/opt_dff_qd.ys index c6232643f..09060a44a 100644 --- a/tests/opt/opt_dff_qd.ys +++ b/tests/opt/opt_dff_qd.ys @@ -29,7 +29,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load orig opt_dff -keepdc diff --git a/tests/opt/opt_dff_sr.ys b/tests/opt/opt_dff_sr.ys index 1d3fd300e..3380a9b2a 100644 --- a/tests/opt/opt_dff_sr.ys +++ b/tests/opt/opt_dff_sr.ys @@ -22,7 +22,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 1 t:$dffsr @@ -35,7 +35,7 @@ select -assert-none t:$sr design -load orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$dffsr @@ -50,7 +50,7 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 1 t:$_DFF_PP0_ @@ -64,7 +64,7 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_ design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$_DFF_PP0_ @@ -109,7 +109,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsre @@ -149,7 +149,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsre @@ -163,7 +163,7 @@ select -assert-count 0 t:$dlatch design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 0 t:$_DFFSR_* select -assert-count 0 t:$_DFFSRE_* @@ -202,7 +202,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsre @@ -242,7 +242,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsre @@ -256,7 +256,7 @@ select -assert-count 0 t:$dlatch design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 0 t:$_DFFSR_* select -assert-count 0 t:$_DFFSRE_* @@ -294,7 +294,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 0 t:$dffsr select -assert-count 0 t:$dffsre diff --git a/tests/opt/opt_dff_srst.ys b/tests/opt/opt_dff_srst.ys index 4a77de0b8..ac362f80e 100644 --- a/tests/opt/opt_dff_srst.ys +++ b/tests/opt/opt_dff_srst.ys @@ -25,7 +25,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-count 0 t:$sdff select -assert-count 0 t:$sdffe @@ -35,7 +35,7 @@ select -assert-count 2 t:$dffe design -load orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 1 t:$sdff select -assert-count 1 t:$sdffe @@ -46,7 +46,7 @@ select -assert-count 1 t:$dffe design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:$_SDFF_???_ select -assert-none t:$_SDFFE_????_ @@ -57,7 +57,7 @@ select -assert-count 4 t:$_DFFE_??_ design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc +equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc design -load postopt select -assert-count 2 t:$_SDFF_???_ select -assert-count 2 t:$_SDFFE_????_ @@ -90,7 +90,7 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:$sdff select -assert-none t:$sdffe @@ -101,7 +101,7 @@ select -assert-count 2 t:$dffe design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff +equiv_opt -nocells -undef -assert -multiclock opt_dff design -load postopt select -assert-none t:$_SDFF_???_ select -assert-none t:$_SDFFE_????_ diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys index fc579e7d6..216d5ee9a 100644 --- a/tests/techmap/dfflegalize_adff.ys +++ b/tests/techmap/dfflegalize_adff.ys @@ -37,12 +37,12 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x # Convert everything to ADFFs. diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys index 25ed59307..595b15ddf 100644 --- a/tests/techmap/dfflegalize_adff_init.ys +++ b/tests/techmap/dfflegalize_adff_init.ys @@ -37,22 +37,22 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to ADFFs. diff --git a/tests/techmap/dfflegalize_adlatch.ys b/tests/techmap/dfflegalize_adlatch.ys index 559363301..b5bf29d41 100644 --- a/tests/techmap/dfflegalize_adlatch.ys +++ b/tests/techmap/dfflegalize_adlatch.ys @@ -21,8 +21,8 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x # Convert everything to ADLATCHs. diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys index 8e371c528..c0e6eb0e8 100644 --- a/tests/techmap/dfflegalize_adlatch_init.ys +++ b/tests/techmap/dfflegalize_adlatch_init.ys @@ -21,12 +21,12 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 # Convert everything to ADLATCHs. diff --git a/tests/techmap/dfflegalize_aldff.ys b/tests/techmap/dfflegalize_aldff.ys index 5be3e9742..fea715f99 100644 --- a/tests/techmap/dfflegalize_aldff.ys +++ b/tests/techmap/dfflegalize_aldff.ys @@ -22,10 +22,10 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x # Convert everything to ALDFFs. diff --git a/tests/techmap/dfflegalize_aldff_init.ys b/tests/techmap/dfflegalize_aldff_init.ys index ffa7cbf16..1c3734feb 100644 --- a/tests/techmap/dfflegalize_aldff_init.ys +++ b/tests/techmap/dfflegalize_aldff_init.ys @@ -22,14 +22,14 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to ALDFFs. diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys index 374289678..edf3b9f75 100644 --- a/tests/techmap/dfflegalize_dff.ys +++ b/tests/techmap/dfflegalize_dff.ys @@ -66,17 +66,17 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x # Convert everything to DFFs. diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys index a170249c7..4878fd19a 100644 --- a/tests/techmap/dfflegalize_dff_init.ys +++ b/tests/techmap/dfflegalize_dff_init.ys @@ -66,38 +66,38 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1 # Convert everything to DFFs. diff --git a/tests/techmap/dfflegalize_dffsr.ys b/tests/techmap/dfflegalize_dffsr.ys index 49a7237a2..6257b3d8e 100644 --- a/tests/techmap/dfflegalize_dffsr.ys +++ b/tests/techmap/dfflegalize_dffsr.ys @@ -24,10 +24,10 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x # Convert everything to ADFFs. diff --git a/tests/techmap/dfflegalize_dffsr_init.ys b/tests/techmap/dfflegalize_dffsr_init.ys index b6160bb87..e61ac5dac 100644 --- a/tests/techmap/dfflegalize_dffsr_init.ys +++ b/tests/techmap/dfflegalize_dffsr_init.ys @@ -41,18 +41,18 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to ADFFs. diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys index 11683bc1a..13cc469ab 100644 --- a/tests/techmap/dfflegalize_dlatch.ys +++ b/tests/techmap/dfflegalize_dlatch.ys @@ -8,11 +8,11 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x # Convert everything to DFFs. diff --git a/tests/techmap/dfflegalize_dlatch_const.ys b/tests/techmap/dfflegalize_dlatch_const.ys index 159692249..db3f90a16 100644 --- a/tests/techmap/dfflegalize_dlatch_const.ys +++ b/tests/techmap/dfflegalize_dlatch_const.ys @@ -14,10 +14,10 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01 -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to ADFFs. diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys index 9324c6691..c982ee67e 100644 --- a/tests/techmap/dfflegalize_dlatch_init.ys +++ b/tests/techmap/dfflegalize_dlatch_init.ys @@ -8,18 +8,18 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 # Convert everything to DFFs. diff --git a/tests/techmap/dfflegalize_dlatchsr.ys b/tests/techmap/dfflegalize_dlatchsr.ys index 53d910723..3083c0f5a 100644 --- a/tests/techmap/dfflegalize_dlatchsr.ys +++ b/tests/techmap/dfflegalize_dlatchsr.ys @@ -10,8 +10,8 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x # Convert everything to ADLATCHs. diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys index da4ca164e..39311496f 100644 --- a/tests/techmap/dfflegalize_dlatchsr_init.ys +++ b/tests/techmap/dfflegalize_dlatchsr_init.ys @@ -23,12 +23,12 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 # Convert everything to ADLATCHs. diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys index a74d74161..16e95fb8f 100644 --- a/tests/techmap/dfflegalize_inv.ys +++ b/tests/techmap/dfflegalize_inv.ys @@ -103,7 +103,7 @@ EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x design -load postopt select -assert-count 51 t:$_NOT_ @@ -134,7 +134,7 @@ select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFS design -load orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x design -load postopt select -assert-count 135 t:$_NOT_ @@ -179,7 +179,7 @@ endmodule EOT -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x design -load postopt select -assert-count 6 t:$_NOT_ diff --git a/tests/techmap/dfflegalize_mince.ys b/tests/techmap/dfflegalize_mince.ys index 31c8d04fc..6dc2c9e5a 100644 --- a/tests/techmap/dfflegalize_mince.ys +++ b/tests/techmap/dfflegalize_mince.ys @@ -22,7 +22,7 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3 design -load postopt select -assert-count 4 t:$_DFFE_PP_ diff --git a/tests/techmap/dfflegalize_minsrst.ys b/tests/techmap/dfflegalize_minsrst.ys index 689066147..093b578f0 100644 --- a/tests/techmap/dfflegalize_minsrst.ys +++ b/tests/techmap/dfflegalize_minsrst.ys @@ -18,7 +18,7 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3 design -load postopt select -assert-count 5 t:$_SDFF_PP0_ diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys index ee59a6e3c..35a7a410f 100644 --- a/tests/techmap/dfflegalize_sr.ys +++ b/tests/techmap/dfflegalize_sr.ys @@ -9,12 +9,12 @@ endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x # Convert everything to SRs. diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys index 7cb1c629d..461b9958a 100644 --- a/tests/techmap/dfflegalize_sr_init.ys +++ b/tests/techmap/dfflegalize_sr_init.ys @@ -21,18 +21,18 @@ EOT design -save orig flatten -equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 -equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to SRs. diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys index 562db0776..5571870c2 100644 --- a/tests/techmap/zinit.ys +++ b/tests/techmap/zinit.ys @@ -19,7 +19,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); endmodule EOT -equiv_opt -assert -multiclock zinit +equiv_opt -nocells -assert -multiclock zinit design -load postopt select -assert-count 16 t:$_NOT_ @@ -52,7 +52,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); endmodule EOT -equiv_opt -assert -multiclock zinit +equiv_opt -nocells -assert -multiclock zinit design -load postopt select -assert-count 0 t:$_NOT_ @@ -95,7 +95,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23])); endmodule EOT -equiv_opt -assert -multiclock zinit +equiv_opt -nocells -assert -multiclock zinit design -load postopt select -assert-count 48 t:$_NOT_ @@ -141,7 +141,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23])); endmodule EOT -equiv_opt -assert -multiclock zinit +equiv_opt -nocells -assert -multiclock zinit design -load postopt select -assert-count 0 t:$_NOT_