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Use equiv_opt -nocells to ensure everything is ok since dffs retain their name

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This commit is contained in:
Akash Levy 2025-01-16 19:40:18 -08:00
parent 67a93dc76d
commit ab338b33cb
30 changed files with 201 additions and 201 deletions
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12
tests/techmap/dfflegalize_adff.ys
View file

@ -37,12 +37,12 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs.

32
tests/techmap/dfflegalize_adff_init.ys
View file

@ -37,22 +37,22 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs.

4
tests/techmap/dfflegalize_adlatch.ys
View file

@ -21,8 +21,8 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_adlatch_init.ys
View file

@ -21,12 +21,12 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs.

8
tests/techmap/dfflegalize_aldff.ys
View file

@ -22,10 +22,10 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ALDFFs.

16
tests/techmap/dfflegalize_aldff_init.ys
View file

@ -22,14 +22,14 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ALDFFs.

22
tests/techmap/dfflegalize_dff.ys
View file

@ -66,17 +66,17 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x
# Convert everything to DFFs.

64
tests/techmap/dfflegalize_dff_init.ys
View file

@ -66,38 +66,38 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1
# Convert everything to DFFs.

8
tests/techmap/dfflegalize_dffsr.ys
View file

@ -24,10 +24,10 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs.

24
tests/techmap/dfflegalize_dffsr_init.ys
View file

@ -41,18 +41,18 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs.

10
tests/techmap/dfflegalize_dlatch.ys
View file

@ -8,11 +8,11 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
# Convert everything to DFFs.

8
tests/techmap/dfflegalize_dlatch_const.ys
View file

@ -14,10 +14,10 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs.

24
tests/techmap/dfflegalize_dlatch_init.ys
View file

@ -8,18 +8,18 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
# Convert everything to DFFs.

4
tests/techmap/dfflegalize_dlatchsr.ys
View file

@ -10,8 +10,8 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_dlatchsr_init.ys
View file

@ -23,12 +23,12 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs.

6
tests/techmap/dfflegalize_inv.ys
View file

@ -103,7 +103,7 @@ EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
design -load postopt
select -assert-count 51 t:$_NOT_
@ -134,7 +134,7 @@ select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFS
design -load orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
design -load postopt
select -assert-count 135 t:$_NOT_
@ -179,7 +179,7 @@ endmodule
EOT
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
design -load postopt
select -assert-count 6 t:$_NOT_

2
tests/techmap/dfflegalize_mince.ys
View file

@ -22,7 +22,7 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
design -load postopt
select -assert-count 4 t:$_DFFE_PP_

2
tests/techmap/dfflegalize_minsrst.ys
View file

@ -18,7 +18,7 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
design -load postopt
select -assert-count 5 t:$_SDFF_PP0_

12
tests/techmap/dfflegalize_sr.ys
View file

@ -9,12 +9,12 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to SRs.

24
tests/techmap/dfflegalize_sr_init.ys
View file

@ -21,18 +21,18 @@ EOT
design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_SR_PP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -nocells -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to SRs.

8
tests/techmap/zinit.ys
View file

@ -19,7 +19,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule
EOT
equiv_opt -assert -multiclock zinit
equiv_opt -nocells -assert -multiclock zinit
design -load postopt
select -assert-count 16 t:$_NOT_
@ -52,7 +52,7 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
endmodule
EOT
equiv_opt -assert -multiclock zinit
equiv_opt -nocells -assert -multiclock zinit
design -load postopt
select -assert-count 0 t:$_NOT_
@ -95,7 +95,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule
EOT
equiv_opt -assert -multiclock zinit
equiv_opt -nocells -assert -multiclock zinit
design -load postopt
select -assert-count 48 t:$_NOT_
@ -141,7 +141,7 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule
EOT
equiv_opt -assert -multiclock zinit
equiv_opt -nocells -assert -multiclock zinit
design -load postopt
select -assert-count 0 t:$_NOT_