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Use equiv_opt -nocells to ensure everything is ok since dffs retain their name

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This commit is contained in:
Akash Levy 2025-01-16 19:40:18 -08:00
parent 67a93dc76d
commit ab338b33cb
30 changed files with 201 additions and 201 deletions
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12
tests/opt/opt_dff_arst.ys
View file

@ -24,13 +24,13 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:*
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$adff
select -assert-count 1 t:$adffe
@ -39,14 +39,14 @@ select -assert-count 1 t:$adlatch
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:*
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 2 t:$_DFF_???_
select -assert-count 2 t:$_DFFE_????_
@ -77,7 +77,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:$adff
select -assert-none t:$adffe
@ -89,7 +89,7 @@ select -assert-count 1 t:$dlatch
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:$_DFF_???_
select -assert-none t:$_DFFE_????_

4
tests/opt/opt_dff_clk.ys
View file

@ -29,7 +29,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 2 t:$dlatch
select -assert-count 2 t:$sr
@ -38,7 +38,7 @@ select -assert-none t:$dlatch t:$sr %% %n t:* %i
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 4 t:$_DLATCH_?_
select -assert-count 4 t:$_SR_??_

2
tests/opt/opt_dff_const.ys
View file

@ -33,7 +33,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 1 t:$dff r:WIDTH=2 %i
select -assert-count 1 t:$dffe r:WIDTH=2 %i

14
tests/opt/opt_dff_dffmux.ys
View file

@ -6,7 +6,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -21,7 +21,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$dffe r:WIDTH=2 %i
@ -37,7 +37,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -52,7 +52,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=4 %i
select -assert-count 0 t:$dffe %% t:* %D
@ -67,7 +67,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -86,7 +86,7 @@ endmodule
EOT
proc
equiv_opt -assert opt
equiv_opt -nocells -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
@ -113,7 +113,7 @@ proc
# instead of `sat -tempinduct-baseonly` or
# `sat -tempinduct` which is necessary for this
# testcase
#equiv_opt -assert opt
#equiv_opt -nocells -assert opt
design -save gold
opt

12
tests/opt/opt_dff_en.ys
View file

@ -30,12 +30,12 @@ design -save orig
# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
delete top/ff6 top/ff7
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load orig
delete top/ff6 top/ff7
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load orig
opt_dff
@ -110,7 +110,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 2 t:$dffe
select -assert-count 4 t:$dlatch
@ -119,7 +119,7 @@ select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 2 t:$dffe
select -assert-count 1 t:$adffe
@ -134,7 +134,7 @@ select -assert-count 2 t:$sr
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 4 t:$_DFFE_??_
select -assert-count 8 t:$_DLATCH_?_
@ -144,7 +144,7 @@ select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 4 t:$_DFFE_??_
select -assert-count 2 t:$_DFFE_????_

8
tests/opt/opt_dff_mux.ys
View file

@ -30,7 +30,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
clean
select -assert-count 0 t:$dff
@ -45,7 +45,7 @@ select -assert-count 2 t:$sdffce
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -nodffe -nosdff
equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe -nosdff
design -load postopt
clean
select -assert-count 1 t:$dff
@ -57,7 +57,7 @@ select -assert-count 1 t:$dffsre
select -assert-count 1 t:$sdff
select -assert-count 1 t:$sdffe
select -assert-count 1 t:$sdffce
equiv_opt -undef -assert -multiclock opt_dff -nodffe
equiv_opt -nocells -undef -assert -multiclock opt_dff -nodffe
design -load postopt
clean
select -assert-count 0 t:$dff
@ -72,7 +72,7 @@ select -assert-count 2 t:$sdffce
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -nosdff
equiv_opt -nocells -undef -assert -multiclock opt_dff -nosdff
design -load postopt
clean
select -assert-count 0 t:$dff

2
tests/opt/opt_dff_qd.ys
View file

@ -29,7 +29,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load orig
opt_dff -keepdc

22
tests/opt/opt_dff_sr.ys
View file

@ -22,7 +22,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 1 t:$dffsr
@ -35,7 +35,7 @@ select -assert-none t:$sr
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$dffsr
@ -50,7 +50,7 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 1 t:$_DFF_PP0_
@ -64,7 +64,7 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$_DFF_PP0_
@ -109,7 +109,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre
@ -149,7 +149,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$dffsr
select -assert-count 1 t:$dffsre
@ -163,7 +163,7 @@ select -assert-count 0 t:$dlatch
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 0 t:$_DFFSR_*
select -assert-count 0 t:$_DFFSRE_*
@ -202,7 +202,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre
@ -242,7 +242,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$dffsr
select -assert-count 1 t:$dffsre
@ -256,7 +256,7 @@ select -assert-count 0 t:$dlatch
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 0 t:$_DFFSR_*
select -assert-count 0 t:$_DFFSRE_*
@ -294,7 +294,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 0 t:$dffsr
select -assert-count 0 t:$dffsre

12
tests/opt/opt_dff_srst.ys
View file

@ -25,7 +25,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-count 0 t:$sdff
select -assert-count 0 t:$sdffe
@ -35,7 +35,7 @@ select -assert-count 2 t:$dffe
design -load orig
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 1 t:$sdff
select -assert-count 1 t:$sdffe
@ -46,7 +46,7 @@ select -assert-count 1 t:$dffe
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:$_SDFF_???_
select -assert-none t:$_SDFFE_????_
@ -57,7 +57,7 @@ select -assert-count 4 t:$_DFFE_??_
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff -keepdc
equiv_opt -nocells -undef -assert -multiclock opt_dff -keepdc
design -load postopt
select -assert-count 2 t:$_SDFF_???_
select -assert-count 2 t:$_SDFFE_????_
@ -90,7 +90,7 @@ EOT
design -save orig
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:$sdff
select -assert-none t:$sdffe
@ -101,7 +101,7 @@ select -assert-count 2 t:$dffe
design -load orig
simplemap
equiv_opt -undef -assert -multiclock opt_dff
equiv_opt -nocells -undef -assert -multiclock opt_dff
design -load postopt
select -assert-none t:$_SDFF_???_
select -assert-none t:$_SDFFE_????_