From ab12fb313b6ff6e60aaeb6d6a5cb77bf136982cd Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 21 Jul 2026 16:52:31 +0200 Subject: [PATCH] ice40_opt: retire the wrapper's ports before reinterpreting it as $lut --- techlibs/ice40/ice40_opt.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index c715b1ccd..b0963350f 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -138,16 +138,19 @@ static void run_ice40_opts(Module *module) module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", module, cell, log_signal(replacement_output)); - cell->type_impl = TW($lut); auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? TW::CI : TW::I3)); - cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) }); - cell->setPort(TW::Y, cell->getPort(TW::O)); + RTLIL::SigSpec sig_a { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) }; + RTLIL::SigSpec sig_y = cell->getPort(TW::O); + cell->unsetPort(TW::A); cell->unsetPort(TW::B); cell->unsetPort(TW::CI); cell->unsetPort(TW::I0); cell->unsetPort(TW::I3); cell->unsetPort(TW::CO); cell->unsetPort(TW::O); + cell->type_impl = TW($lut); + cell->setPort(TW::A, std::move(sig_a)); + cell->setPort(TW::Y, std::move(sig_y)); cell->setParam(ID::WIDTH, 4); cell->unsetParam(ID(I3_IS_CI)); }