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Merge https://github.com/cliffordwolf/yosys

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This commit is contained in:
Andrew Zonenberg 2016-04-22 19:07:55 -07:00
commit ab11f2aa70
118 changed files with 497 additions and 202 deletions
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2
techlibs/common/prep.cc
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@ -120,7 +120,7 @@ struct PrepPass : public Pass {
bool active = run_from.empty();
log_header("Executing PREP pass.\n");
log_header(design, "Executing PREP pass.\n");
log_push();
if (check_label(active, run_from, run_to, "begin"))

2
techlibs/common/synth.cc
View file

@ -132,7 +132,7 @@ struct SynthPass : public ScriptPass
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
log_header("Executing SYNTH pass.\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();
run_script(design, run_from, run_to);

2
techlibs/greenpak4/greenpak4_counters.cc
View file

@ -408,7 +408,7 @@ struct Greenpak4CountersPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
techlibs/greenpak4/synth_greenpak4.cc
View file

@ -169,7 +169,7 @@ struct SynthGreenPAK4Pass : public Pass {
bool active = run_from.empty();
log_header("Executing SYNTH_GREENPAK4 pass.\n");
log_header(design, "Executing SYNTH_GREENPAK4 pass.\n");
log_push();
if (check_label(active, run_from, run_to, "begin"))

2
techlibs/ice40/ice40_ffinit.cc
View file

@ -37,7 +37,7 @@ struct Ice40FfinitPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ICE40_FFINIT pass (implement FF init values).\n");
log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
techlibs/ice40/ice40_ffssr.cc
View file

@ -35,7 +35,7 @@ struct Ice40FfssrPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

8
techlibs/ice40/ice40_opt.cc
View file

@ -137,7 +137,7 @@ struct Ice40OptPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
string opt_expr_args = "-mux_undef -undriven";
log_header("Executing ICE40_OPT pass (performing simple optimizations).\n");
log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
log_push();
size_t argidx;
@ -154,7 +154,7 @@ struct Ice40OptPass : public Pass {
{
design->scratchpad_unset("opt.did_something");
log_header("Running ICE40 specific optimizations.\n");
log_header(design, "Running ICE40 specific optimizations.\n");
for (auto module : design->selected_modules())
run_ice40_opts(module);
@ -166,14 +166,14 @@ struct Ice40OptPass : public Pass {
if (design->scratchpad_get_bool("opt.did_something") == false)
break;
log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n");
}
design->optimize();
design->sort();
design->check();
log_header("Finished OPT passes. (There is nothing left to do.)\n");
log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");
log_pop();
}
} Ice40OptPass;

2
techlibs/ice40/synth_ice40.cc
View file

@ -149,7 +149,7 @@ struct SynthIce40Pass : public ScriptPass
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
log_header("Executing SYNTH_ICE40 pass.\n");
log_header(design, "Executing SYNTH_ICE40 pass.\n");
log_push();
run_script(design, run_from, run_to);

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -160,7 +160,7 @@ struct SynthXilinxPass : public Pass {
bool active = run_from.empty();
log_header("Executing SYNTH_XILINX pass.\n");
log_header(design, "Executing SYNTH_XILINX pass.\n");
log_push();
if (check_label(active, run_from, run_to, "begin"))