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Added GP_VREF cell

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Andrew Zonenberg 2016-04-20 20:48:19 -07:00
parent bf64974d43
commit d90c1e9522
1 changed files with 6 additions and 0 deletions
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6
techlibs/greenpak4/cells_sim.v
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@ -263,6 +263,12 @@ module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
module GP_VSS(output OUT);
assign OUT = 0;
endmodule