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ice40_dsp: group empty wires

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This commit is contained in:
Anhijkt 2025-03-16 15:11:45 +02:00
parent 5ae32efca5
commit a9d765e11e
1 changed files with 8 additions and 3 deletions
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11
techlibs/ice40/ice40_dsp.pmg
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@ -53,11 +53,16 @@ code sigA sigB sigH
if (i == 0) if (i == 0)
reject; reject;
for (int j = 0; j <= i; j++) for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0) if (nusers(O[j]) == 0)
sigH.append(module->addWire(NEW_ID)); wire_width++;
else else {
if (wire_width) { // add empty wires for bit offset if needed
sigH.append(module->addWire(NEW_ID, wire_width));
wire_width = 0;
}
sigH.append(O[j]); sigH.append(O[j]);
}
endcode endcode