From a9d765e11ef04fda65de4027f1d4b5fa87370f0f Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Sun, 16 Mar 2025 15:11:45 +0200
Subject: [PATCH] ice40_dsp: group empty wires

---
 techlibs/ice40/ice40_dsp.pmg | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg
index 285e3ceee..63bc8de4b 100644
--- a/techlibs/ice40/ice40_dsp.pmg
+++ b/techlibs/ice40/ice40_dsp.pmg
@@ -53,11 +53,16 @@ code sigA sigB sigH
 	if (i == 0)
 		reject;
 
-	for (int j = 0; j <= i; j++) 
+	for (int j = 0, wire_width = 0; j <= i; j++) 
 		if (nusers(O[j]) == 0)
-			sigH.append(module->addWire(NEW_ID));
-		else
+			wire_width++;
+		else {
+			if (wire_width) { // add empty wires for bit offset if needed
+				sigH.append(module->addWire(NEW_ID, wire_width));
+				wire_width = 0;
+			}
 			sigH.append(O[j]);
+		}
 
 endcode