mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-23 04:38:55 +00:00
Code Activity

sv: fix two struct access bugs

Browse source 
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
This commit is contained in:
Zachary Snow 2021-06-22 10:39:57 -04:00 • committed by Zachary Snow
parent 1aab608cff
commit a9c8ca21d5
5 changed files with 102 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/verilog/struct_access.ys Normal file
View file

@ -0,0 +1,4 @@
read_verilog -formal -sv struct_access.sv
proc
opt -full
sat -verify -seq 1 -prove-asserts -show-all