mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 17:14:08 +00:00
- preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
5 lines
101 B
Plaintext
5 lines
101 B
Plaintext
read_verilog -formal -sv struct_access.sv
|
|
proc
|
|
opt -full
|
|
sat -verify -seq 1 -prove-asserts -show-all
|