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ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech

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Miodrag Milanovic 2023-08-22 10:50:11 +02:00
parent 4a475fa7a2
commit a8809989c4
6 changed files with 17 additions and 16 deletions
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14
passes/opt/opt_lut_ins.cc
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@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass {
log("\n");
log(" -tech <technology>\n");
log(" Instead of generic $lut cells, operate on LUT cells specific\n");
log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n");
log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass {
}
extra_args(args, argidx, design);
if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
for (auto module : design->selected_modules())
@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass {
output = cell->getPort(ID::O);
else
output = cell->getPort(ID::F);
} else if (techname == "ecp5") {
} else if (techname == "lattice" || techname == "ecp5") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
if (!doit)
continue;
log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
if (techname == "ecp5") {
if (techname == "lattice" || techname == "ecp5") {
// Pad the LUT to 4 inputs, adding consts from the front.
int extra = 4 - GetSize(new_inputs);
log_assert(extra >= 0);
@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass {
}
new_lut[i] = lut[lidx];
}
// For ecp5, and gowin do not replace with a const driver — the nextpnr
// For lattice, and gowin do not replace with a const driver — the nextpnr
// packer requires a complete set of LUTs for wide LUT muxes.
if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {
if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") {
// const driver.
remove_cells.push_back(cell);
module->connect(output, new_lut[0]);
@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass {
cell->setParam(ID::LUT, new_lut);
cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs);
} else if (techname == "ecp5") {
} else if (techname == "lattice" || techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4);
cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]);