From a8809989c4f31e284a2bed593d71e9a11deec771 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 22 Aug 2023 10:50:11 +0200 Subject: [PATCH] ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech --- passes/opt/opt_lut_ins.cc | 14 +++++++------- techlibs/ecp5/Makefile.inc | 2 +- techlibs/ecp5/synth_ecp5.cc | 4 ++-- techlibs/lattice/Makefile.inc | 1 + .../{ecp5/ecp5_gsr.cc => lattice/lattice_gsr.cc} | 10 +++++----- techlibs/machxo2/synth_machxo2.cc | 2 +- 6 files changed, 17 insertions(+), 16 deletions(-) create mode 100644 techlibs/lattice/Makefile.inc rename techlibs/{ecp5/ecp5_gsr.cc => lattice/lattice_gsr.cc} (93%) diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 2f7c392b2..652fce1e2 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass { log("\n"); log(" -tech \n"); log(" Instead of generic $lut cells, operate on LUT cells specific\n"); - log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n"); + log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass { } extra_args(args, argidx, design); - if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin") + if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); for (auto module : design->selected_modules()) @@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass { output = cell->getPort(ID::O); else output = cell->getPort(ID::F); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { if (cell->type == ID(LUT4)) { inputs = { cell->getPort(ID::A), @@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass { if (!doit) continue; log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs)); - if (techname == "ecp5") { + if (techname == "lattice" || techname == "ecp5") { // Pad the LUT to 4 inputs, adding consts from the front. int extra = 4 - GetSize(new_inputs); log_assert(extra >= 0); @@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass { } new_lut[i] = lut[lidx]; } - // For ecp5, and gowin do not replace with a const driver — the nextpnr + // For lattice, and gowin do not replace with a const driver — the nextpnr // packer requires a complete set of LUTs for wide LUT muxes. - if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") { + if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") { // const driver. remove_cells.push_back(cell); module->connect(output, new_lut[0]); @@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass { cell->setParam(ID::LUT, new_lut); cell->setParam(ID::WIDTH, GetSize(new_inputs)); cell->setPort(ID::A, new_inputs); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { log_assert(GetSize(new_inputs) == 4); cell->setParam(ID::INIT, new_lut); cell->setPort(ID::A, new_inputs[0]); diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index f9fa79ab9..a1c9bfc52 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -1,5 +1,5 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o +OBJS += techlibs/ecp5/synth_ecp5.o $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh)) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 82e234868..fdc36e552 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -359,7 +359,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_gsr"); + run("lattice_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } @@ -404,7 +404,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)"); else if (!vpr) run("techmap -map +/ecp5/cells_map.v"); - run("opt_lut_ins -tech ecp5"); + run("opt_lut_ins -tech lattice"); run("clean"); } diff --git a/techlibs/lattice/Makefile.inc b/techlibs/lattice/Makefile.inc new file mode 100644 index 000000000..b198de0cc --- /dev/null +++ b/techlibs/lattice/Makefile.inc @@ -0,0 +1 @@ +OBJS += techlibs/lattice/lattice_gsr.o diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/lattice/lattice_gsr.cc similarity index 93% rename from techlibs/ecp5/ecp5_gsr.cc rename to techlibs/lattice/lattice_gsr.cc index 62b231aab..d7d41eca5 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -24,13 +24,13 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct Ecp5GsrPass : public Pass { - Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { } +struct LatticeGsrPass : public Pass { + LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" ecp5_gsr [options] [selection]\n"); + log(" lattice_gsr [options] [selection]\n"); log("\n"); log("Trim active low async resets connected to GSR and resolve GSR parameter,\n"); log("if a GSR or SGSR primitive is used in the design.\n"); @@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n"); + log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass { } } -} Ecp5GsrPass; +} LatticeGsrPass; PRIVATE_NAMESPACE_END diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc index 2b684a7d8..907c6659e 100644 --- a/techlibs/machxo2/synth_machxo2.cc +++ b/techlibs/machxo2/synth_machxo2.cc @@ -239,7 +239,7 @@ struct SynthMachXO2Pass : public ScriptPass run("techmap -D NO_LUT -map +/machxo2/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_gsr"); + run("lattice_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); }