Add check_mem command

Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.

tests/check_mem/bad_il.ys

@@ -0,0 +1,47 @@
+read_rtlil << EOF
+module \top
+  wire input 1 \clk
+  wire output 1 \o
+  memory size 2 offset 1 \my_array
+  cell $meminit \bad_init
+    parameter \WORDS 1
+    parameter \MEMID "\\my_array"
+    parameter \ABITS 32
+    parameter \WIDTH 1
+    parameter \PRIORITY 1
+    connect \ADDR 0
+    connect \DATA 1'0
+  end
+  cell $memwr \bad_wr
+    parameter \MEMID "\\my_array"
+    parameter \CLK_ENABLE 1
+    parameter \CLK_POLARITY 1
+    parameter \PRIORITY 1
+    parameter \ABITS 2
+    parameter \WIDTH 1
+    connect \EN 1'1
+    connect \CLK \clk
+    connect \ADDR 2'00
+    connect \DATA 1'0
+  end
+  cell $memrd \bad_rd
+    parameter \MEMID "\\my_array"
+    parameter \CLK_ENABLE 0
+    parameter \CLK_POLARITY 1
+    parameter \TRANSPARENT 0
+    parameter \ABITS 2
+    parameter \WIDTH 1
+    connect \CLK 1'x
+    connect \EN 1'x
+    connect \ADDR 2'11
+    connect \DATA \o
+  end
+end
+EOF
+
+logger -expect warning "initializes address 0" 1
+logger -expect warning "writes address 0" 1
+logger -expect warning "reads address 3" 1
+check_mem
+logger -check-expected
+design -reset

tests/check_mem/generate_mk.py

@@ -0,0 +1,8 @@
+#!/usr/bin/env python3
+
+import sys
+sys.path.append("..")
+
+import gen_tests_makefile
+
+gen_tests_makefile.generate(["--check-sv", "--yosys-scripts"], yosys_cmds="hierarchy; proc; check_mem -assert")

tests/check_mem/init.sv

@@ -0,0 +1,15 @@
+module top (
+  input logic clk,
+  input logic idx,
+  output logic [2:0] out_data
+);
+  (* nomem2reg *)
+  logic my_array [3:2][2:0] = '{'{0, 1, 1}, '{1, 0, 1}};
+
+  always_comb begin
+    for (int i=0; i < 3; i++) begin
+        out_data[i] = my_array[{1'b1, idx}][i];
+    end
+  end
+
+endmodule

tests/check_mem/non_zero.sv

@@ -0,0 +1,21 @@
+module top (
+  input logic clk,
+  input logic [3:1][2:0] in_data,
+  output logic [3:1][2:0] out_data
+);
+  (* nomem2reg *)
+  logic [2:0] my_array [3:1];
+
+  always_ff @(posedge clk) begin
+    for (int i = 1; i <= 3; i++) begin
+      my_array[i] <= in_data[i];
+    end
+  end
+
+  always_comb begin
+    for (int i = 1; i <= 3; i++) begin
+      out_data[i] = my_array[i];
+    end
+  end
+
+endmodule

tests/check_mem/power_of_two.sv

@@ -0,0 +1,24 @@
+module top (
+  input logic clk,
+  input logic [1:0][5:0] in_data,
+  output logic [1:0][5:0] out_data
+);
+  (* nomem2reg *)
+  logic my_array [1:0][5:0];
+
+  always_ff @(posedge clk) begin
+    for (int i = 0; i < 2; i++) begin
+      for (int j = 0; j <= 5; j++) begin
+        my_array[i][j] <= in_data[i][j];
+      end
+    end
+  end
+
+  always_comb begin
+    for (int i = 0; i < 2; i++) begin
+      for (int j = 0; j <= 5; j++) begin
+        out_data[i][j] = my_array[i][j];
+      end
+    end
+  end
+endmodule